Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.

Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a diaphragm, a backplate and a first protrusion. The substrate has an opening portion. The diaphragm is disposed on one side of the substrate and extends across the opening portion of the substrate. The backplate includes a plurality of acoustic holes. The backplate is disposed on one side of the diaphragm. An air gap is formed between the backplate and the diaphragm. The first protrusion extends from the backplate towards the air gap.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: The disclosure provides a method for fabricating a semiconductor structure with strengthened patterns. The method includes forming a masking layer on the substrate, the masking layer including a peripheral region and an array region adjacent to the peripheral region; forming a first etched peripheral pattern in the peripheral region and a first etched array pattern in the array region, wherein the first etched peripheral pattern and the first etched array pattern have a top surface, a sidewall and a bottom surface, the sidewall connecting the top surface to the bottom surface; forming a second peripheral pattern on the first etched peripheral pattern and forming a second array pattern on the first etched array pattern; and etching the masking layer using the first etched peripheral pattern and the second peripheral pattern as an etching mask to form an etched masking layer in the peripheral region.

Abstract: A semiconductor structure includes a substrate, a bit line, a dielectric layer and a word line. The substrate has an active area and a trench. The bit line is on the substrate and extends along a direction. The active area includes a first portion and a second portion respectively located at two opposite sides of the bit line and spaced apart from each other along the direction. A landing area extends from the first portion of the active area to the second portion of the active area across the bit line. A dielectric layer is in the trench. The active area is surrounded by the dielectric layer. The word line is surrounded by the dielectric layer. The word line is curved and below the bit line. A portion of the word line is between first and second end portions of the landing area.

Abstract: A semiconductor structure includes a substrate, a bit line, a dielectric layer and a word line. The substrate has an active area and a trench. The bit line is on the substrate and extends along a direction. The active area includes a first portion and a second portion respectively located at two opposite sides of the bit line and spaced apart from each other along the direction. A landing area extends from the first portion of the active area to the second portion of the active area across the bit line. A dielectric layer is in the trench. The active area is surrounded by the dielectric layer. The word line is surrounded by the dielectric layer. The word line is curved and below the bit line. A portion of the word line is between first and second end portions of the landing area.

Abstract: The disclosure provides a double patterning technology to define peripheral patterns in a DRAM cell. Due to the consideration of line width, the peripheral pattern lines need to undergo two lithographic processes and two etch processes. The presence of additional photoresist patterns in the array region while fabricating peripheral patterns on the M0 layer can increase the stability of peripheral pattern lines. Peripheral pattern lines will not collapse after being subjected to the rinse of developing agent. Moreover, the photoresist coverage of patterns in the array region is not excessive, so the loading effect during etch processes is reduced and the occurrence of photoresist residues is avoided.

Abstract: The disclosure provides a method for fabricating a semiconductor structure with strengthened patterns. The method includes forming a masking layer on the substrate, the masking layer including a peripheral region and an array region adjacent to the peripheral region; forming a first etched peripheral pattern in the peripheral region and a first etched array pattern in the array region, wherein the first etched peripheral pattern and the first etched array pattern have a top surface, a sidewall and a bottom surface, the sidewall connecting the top surface to the bottom surface; forming a second peripheral pattern on the first etched peripheral pattern and forming a second array pattern on the first etched array pattern; and etching the masking layer using the first etched peripheral pattern and the second peripheral pattern as an etching mask to form an etched masking layer in the peripheral region.

Abstract: The disclosure provides a double patterning technology to define peripheral patterns in a DRAM cell. Due to the consideration of line width, the peripheral pattern lines need to undergo two lithographic processes and two etch processes. The presence of additional photoresist patterns in the array region while fabricating peripheral patterns on the M0 layer can increase the stability of peripheral pattern lines. Peripheral pattern lines will not collapse after being subjected to the rinse of developing agent. Moreover, the photoresist coverage of patterns in the array region is not excessive, so the loading effect during etch processes is reduced and the occurrence of photoresist residues is avoided.

Abstract: A method for determining orientation of an electrical resistivity boundary in a wellbore includes using measurements of an electromagnetic property of formations traversed by the wellbore at at least one axial spacing between a multiaxial electromagnetic transmitter and a multiaxial electromagnetic receiver, and determining a symmetrized angle using measurements of the electromagnetic property made using receiver components transverse to a well logging instrument axis and a transmitter component along the axis. At least a relative orientation of the electrical boundary with respect to an orientation of the well logging instrument is determined using the symmetrized angle.

Abstract: A method includes introducing a tool into a wellbore lined at least partially with a first casing and a second casing concentrically overlapping a portion of the first casing emitting an acoustic wave from an acoustic source included in the tool causing the first and second casings to vibrate at their respective resonant frequencies, emitting high frequency electromagnetic (EM) energy using the tool that interacts with the first casing to generate a first EM scattered field, emitting low frequency EM energy using the tool, at least a portion of the low frequency EM energy traversing the first casing and interacting with the second casing to generate a second EM scattered field, and analyzing the first and second EM scattered fields to determine a presence of corrosion in at least one of the first and second casings.

Abstract: A method includes introducing a tool into a wellbore lined at least partially with a first casing and a second casing concentrically overlapping a portion of the first casing emitting an acoustic wave from an acoustic source included in the tool causing the first and second casings to vibrate at their respective resonant frequencies, emitting high frequency electromagnetic (EM) energy using the tool that interacts with the first casing to generate a first EM scattered field, emitting low frequency EM energy using the tool, at least a portion of the low frequency EM energy traversing the first casing and interacting with the second casing to generate a second EM scattered field, and analyzing the first and second EM scattered fields to determine a presence of corrosion in at least one of the first and second casings.

Abstract: A method for determining orientation of an electrical resistivity boundary in a wellbore includes using measurements of an electromagnetic property of formations traversed by the wellbore at at least one axial spacing between a multiaxial electromagnetic transmitter and a multiaxial electromagnetic receiver, and determining a symmetrized angle using measurements of the electromagnetic property made using receiver components transverse to a well logging instrument axis and a transmitter component along the axis. At least a relative orientation of the electrical boundary with respect to an orientation of the well logging instrument is determined using the symmetrized angle.

Abstract: This invention discloses a stackable connector assembly, which includes a first connector, a second connector, a shielding member, a contact member, and a ground member. The second connector is placed above the first connector. The shielding member is covered on the first connector. The contact member is used for connecting the shielding member and the ground member. This structure can reduce the electromagnetic radiation from the first connector.

Abstract: This invention discloses a stackable connector assembly, which includes a first connector, a second connector, a shielding member, a contact member, and a ground member. The second connector is placed above the first connector. The shielding member is covered on the first connector. The contact member is used for connecting the shielding member and the ground member. This structure can reduce the electromagnetic radiation from the first connector.

Abstract: This invention discloses a stackable connector assembly, which includes a first connector, a second connector, a shielding member, a contact member, and a ground member. The second connector is placed above the first connector. The shielding member is covered on the first connector. The contact member is used for connecting the shielding member and the ground member. This structure can reduce the electromagnetic radiation from the first connector.

Abstract: This invention discloses a stackable connector assembly, which includes a first connector, a second connector, a shielding member, a contact member, and a ground member. The second connector is placed above the first connector. The shielding member is covered on the first connector. The contact member is used for connecting the shielding member and the ground member. This structure can reduce the electromagnetic radiation from the first connector.