Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.

Abstract: A display device includes a plurality of sub-pixels. The sub-pixels include a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light emitting element and a first control circuit. The first control circuit is configured to provide a first driving current to the first light emitting element. The second sub-pixel includes a second light emitting element and a second control circuit. The second control circuit is configured to provide a second driving current to the second light emitting element. The first control circuit and the second control circuit are configured to differently control pulse amplitude of the first driving current and pulse amplitude of the second driving current, such that both of the first light emitting element and the second light emitting element emit at a target wavelength or a color point range (e.g. +/?1.5˜2 nm).

Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.

Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A enhanced DLL includes a delay chain, a phase detector and a delay control unit. The delay chain is arranged to delay a reference clock signal to generate a delayed reference clock signal and reflect the delay control setting on the delayed reference clock signal, wherein the delay chain is periodically reset according to a period of the reference clock signal. The phase detector is coupled to the delay chain, and arranged to detect a phase shift between the delayed reference clock signal and the reference clock signal, thereby to generate a control value. The delay control unit is coupled to the delay chain and the phase detector, and arranged to adjust the delay control setting based on the control value.

Abstract: The present invention provides a sub-WSN for an IoT system having at least a sensor node, and a sub-sensor node and a sub-gateway for the sub-WSN, so as to solve the problems of low channel quantity and high power consumption in the prior art. The sub-WSN comprises: a sub-gateway and a plurality of sub-sensor nodes. The sub-gateway is wiredly coupled to the Sensor node. The sub-sensor nodes are utilized for sensing and wirelessly communicating with the sub-gateway via RF signals.

Abstract: A method for controlling charge states of a plurality of battery cells connected in series comprises: for a charge node of each battery cells, comparing a voltage of the charge node with a plurality of reference voltages to generate a comparison result, wherein the comparison result comprises a plurality of digital values, respectively; determining a charge state of each battery cell by calculating a difference between the comparison results of two charge nodes of two adjacent battery cells; and controlling charge currents supplied to the battery cells according the charge states of the battery cells, respectively.

Abstract: A resistive random access memory device includes: a first control line, a second control line, a RRAM cell, a first programmable current source and a first programmable voltage source. The RRAM cell is coupled between the first control line and the second control line, and has a programmable resistive element. The first programmable current source is coupled to the first control line, and for selectively providing a configuration current to the RRAM cell. The first programmable voltage source is coupled to the first control line, and for selectively providing a configuration voltage to the RRAM cell. Additionally, a state of the programmable resistive element of the RRAM cell is configured according to the configuration current and the configuration voltage. Under architecture of the RRAM cell of the present invention, a reading circuit for the RRAM device can be implemented with a simple inverter instead of a complicated current sensing amplifier.

Abstract: A resistive random access memory device includes: a first control line, a second control line, a RRAM cell, a first programmable current source and a first programmable voltage source. The RRAM cell is coupled between the first control line and the second control line, and has a programmable resistive element. The first programmable current source is coupled to the first control line, and for selectively providing a configuration current to the RRAM cell. The first programmable voltage source is coupled to the first control line, and for selectively providing a configuration voltage to the RRAM cell. Additionally, a state of the programmable resistive element of the RRAM cell is configured according to the configuration current and the configuration voltage. Under architecture of the RRAM cell of the present invention, a reading circuit for the RRAM device can be implemented with a simple inverter instead of a complicated current sensing amplifier.

Abstract: A dipole antenna array includes a dielectric substrate; electric tuning elements mounted on a first surface and a second surface of the dielectric substrate; resonance elements and ground elements; and a feed line. Each resonance element includes first resonance parts, second resonance parts and a third resonance part. One of the second resonance parts connects the corresponding first resonance part to the third resonance part. The other second resonance parts respectively connect two neighboring first resonance parts. Each ground element includes first ground parts, second ground parts and a third ground part. One of the second ground parts connects one of the first ground parts to the third ground part. The other second ground parts respectively connect to two neighboring first ground parts.

Abstract: A chip-type antenna for receiving FM broadcasting signal includes a ceramic substrate, a ferrite layer formed on a top surface of the ceramic substrate, and a radiation structure. The ceramic substrate and the ferrite layer form an antenna substrate. The radiation structure is formed on the antenna substrate. The chip-type antenna for receiving FM broadcasting signal utilizes the high dielectric constant of the ceramic substrate and the electric characteristic of the ferrite layer to reduce the dimension of the antenna.

Abstract: A dipole antenna array includes a dielectric substrate; electric tuning elements mounted on a first surface and a second surface of the dielectric substrate; resonance elements and ground elements; and a feed line. Each resonance element includes first resonance parts, second resonance parts and a third resonance part. One of the second resonance parts connects the corresponding first resonance part to the third resonance part. The other second resonance parts respectively connect two neighboring first resonance parts. Each ground element includes first ground parts, second ground parts and a third ground part. One of the second ground parts connects one of the first ground parts to the third ground part. The other second ground parts respectively connect to two neighboring first ground parts.

Abstract: A frequency synthesizer applied to a frequency hopping system includes a voltage controlled oscillator (VCO), a phase lock loop (PLL) system, a second frequency divider, a first SSB mixer, a second SSB mixer, and a multiplexer. The VCO generates an oscillating frequency. The PLL system includes a first frequency divider and divides the oscillating frequency by 10 to generate a first dividing signal. The second frequency divider divides the oscillating frequency by 2 to generate a second dividing signal and further divides the second dividing signal by 2 to generate a third dividing signal. The first SSB mixer mixes frequencies of the second and third dividing signals to generate a first mixing signal. The second SSB mixer mixes frequencies of the first mixing signal and the first dividing signal to generate a second mixing signal. The Multiplexer determines to output the first mixing signal or the second mixing signal.

Abstract: A frequency synthesizer applied to a digital television tuner includes: a voltage controlled oscillator (VCO), a phase locked loop (PLL), a frequency divider unit, and a multiplexer. The maximum oscillated frequency of the VCO is twice its minimum frequency. The PLL controls and locks the VCO output frequency by a frequency control signal. The frequency divider unit includes a plurality of first dividers which form a cascade connection. The frequency divider unit receives the VCO output frequency, and subsequently divides the output frequency one by one. The multiplexer receives the dividing signals, and then chooses one of the dividing signals by a frequency selection signal, and generates a local oscillation signal. Hence, the present invention can implement the frequency synthesizer by simple architecture and cover the frequency ranges of Digital Video Broadcasting standard.

Abstract: A frequency synthesizer applied to a frequency hopping system includes a voltage controlled oscillator (VCO), a phase lock loop (PLL) system, a second frequency divider, a first SSB mixer, a second SSB mixer, and a multiplexer. The VCO generates an oscillating frequency. The PLL system includes a first frequency divider and divides the oscillating frequency by 10 to generate a first dividing signal. The second frequency divider divides the oscillating frequency by 2 to generate a second dividing signal and further divides the second dividing signal by 2 to generate a third dividing signal. The first SSB mixer mixes frequencies of the second and third dividing signals to generate a first mixing signal. The second SSB mixer mixes frequencies of the first mixing signal and the first dividing signal to generate a second mixing signal. The Multiplexer determines to output the first mixing signal or the second mixing signal.

Abstract: A method for I/Q adjustment is disclosed. The method includes delaying phases of an in-phase signal and a quadrature signal with a predetermined angle for generating an in-phase delay signal and a quadrature delay signal; adjusting magnitudes of the in-phase signal, the quadrature signal, the in-phase delay signal, and the quadrature delay signal according to a magnitude difference signal and a phase control signal; adding the adjusted in-phase signal and the adjusted in-phase delay signal; and adding the adjusted quadrature signal and the adjusted quadrature delay signal.

Abstract: A linear tuning varactor circuit has the first single-end varactor circuit, the second single-end varactor circuit and a voltage divider. The first single-end varactor circuit has tuning terminal receiving the tuning voltage to change the capacitance thereof The second single-end varactor circuit has a reference voltage terminal receiving the reference with constant voltage. The first single-end varactor circuit and the second single-end varactor circuit are coupled to each other in series and have a node. The voltage divider is coupled to the tuning terminal, the reference voltage terminal and the node. The node has a divided voltage, which results from dividing a voltage difference between the tuning voltage and the reference voltage by the voltage divider with a pre-set voltage dividing ratio.

Abstract: A linear tuning varactor circuit has the first single-end varactor circuit, the second single-end varactor circuit and a voltage divider. The first single-end varactor circuit has tuning terminal receiving the tuning voltage to change the capacitance thereof The second single-end varactor circuit has a reference voltage terminal receiving the reference with constant voltage. The first single-end varactor circuit and the second single-end varactor circuit are coupled to each other in series and have a node. The voltage divider is coupled to the tuning terminal, the reference voltage terminal and the node. The node has a divided voltage, which results from dividing a voltage difference between the tuning voltage and the reference voltage by the voltage divider with a pre-set voltage dividing ratio.