Patents by Inventor Chih-Hao Pan

Chih-Hao Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210234036
    Abstract: A semiconductor device structure includes a fin structure, a semiconductive capping layer, an oxide layer, and a gate structure. The fin structure protrudes above a substrate. The semiconductive capping layer wraps around three sides of a channel region of the fin structure. The oxide layer wraps around three sides of the semiconductive capping layer. A thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer. The gate structure wraps around three sides of the oxide layer.
    Type: Application
    Filed: April 17, 2021
    Publication date: July 29, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Kuan-Ting PAN, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20210226036
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked nanostructure and a second stacked nanostructure extending above the isolation structure. The semiconductor device structure includes an inner spacer layer surrounding the first stacked nanostructure, and a dummy fin structure formed over the isolation structure. The dummy fin structure is between the first stacked nanostructure and the second stacked nanostructure, and a capping layer formed over the dummy fin structure. The inner spacer layer is in direct contact with the dummy fin structure and the capping layer.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng CHING, Zhi-Chang LIN, Kuan-Ting PAN, Chih-Hao WANG, Shi-Ning JU
  • Patent number: 11062968
    Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Publication number: 20210134979
    Abstract: A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 6, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng
  • Patent number: 10580780
    Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 3, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Zi-Jun Liu, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Hung-Wei Lin, An-Hsiu Cheng, Chih-Hao Pan, Cheng-Hua Chou, Chih-Hung Wang
  • Publication number: 20190378846
    Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 12, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Zi-Jun Liu, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Hung-Wei Lin, An-Hsiu Cheng, Chih-Hao Pan, Cheng-Hua Chou, Chih-Hung Wang
  • Patent number: 10340282
    Abstract: A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: July 2, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Hung Yu, Chun-Hung Cheng, Chuan-Fu Wang, An-Hsiu Cheng, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Chia-Hui Huang, Chih-Yao Wang, Zi-Jun Liu, Chih-Hao Pan
  • Publication number: 20190043877
    Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 7, 2019
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Wen-Peng Hsu, Chia-Wen Wang, Meng-Chun Chen, Chih-Hao Pan
  • Patent number: 10199385
    Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Wen-Peng Hsu, Chia-Wen Wang, Meng-Chun Chen, Chih-Hao Pan
  • Patent number: 6445087
    Abstract: A power plug device has a power plug, at least one switched power socket at least one socket switch, a embedded controller and a telephone jack. The embedded controller can send and receive network signals across a telephone line through the telephone jack, or across a power line through the power plug of the power plug device. The power plug device may switch on or off its power sockets depending on networking signals that come from the power or telephone lines. The power plug device can also send networking signals out along the telephone or power line. The power plug device also has a networking communications port. Two such power plug devices enable two or more computers to communicate with each other using the existing power and telephone lines within a building.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: September 3, 2002
    Assignee: Primax Electronics Ltd.
    Inventors: Jong-Ding Wang, Chih-Hao Pan
  • Patent number: 6364680
    Abstract: A thin line jack expansion module clips onto and electrically connects to a thin line expansion cable. The thin line expansion cable has signal lines for transmitting communications signals. The expansion module has an internal module and an external module. The internal module has a cable bay for accommodating the thin line expansion cable, cable contacts in the cable bay for establishing electrical connections with the signal lines of the thin line expansion cable, and a jack. The jack is electrically connected to the cable contacts. The external module clips onto the internal module and at least partially covers the cable bay. When the thin line expansion cable is set in the cable bay, and the external module is snapped onto the internal module, the cable contacts will electrically connect the jack to the signal lines within the thin line expansion cable.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: April 2, 2002
    Assignee: Primax Electronics Ltd.
    Inventors: Sen-Hsiang Liu, Chih-Hao Pan, Wei-Chen Tu, Dongfeng Ku