Patents by Inventor Chih-Hao Sun

Chih-Hao Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RADIO FREQUENCY MODULATOR AND METHOD THEREOF
    Publication number: 20110193606
    Abstract: A radio frequency (RF) modulator includes: converting means for up-converting a first and second baseband signals into a first and second up-converted signals with a reference clock, wherein a phase difference between the first and second baseband signals substantially equals 180°/N; and combining means for combining the first and second up-converted signals to generate an output signal.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 11, 2011
    Inventor: Chih-Hao Sun
  • Voltage-controlled delay line with reduced timing errors and jitters
    Patent number: 6756818
    Abstract: A voltage controlled delay line having a plurality of delay cells is used to delay a first reference clock by a predetermined delay time to generate an in-phase first delay clock and to delay a second reference clock by the predetermined delay time to generate an in-phase second delay clock. Each delay cell has a first input port, a second input port, a first output port, and a second output port. The first output port of one delay cell and the second input port of another one delay cell having the same phase are electrically connected or the second output port of one delay cell and the first input port of another one delay cell having the same phase are electrically connected so that the first and second input port of each delay cell are not connected to the first and second output port of an adjacent delay cell.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: June 29, 2004
    Assignee: Mediatek Incorporation
    Inventors: Shen-Iuan Liu, Chih-Hao Sun, Hsiang-Hui Chang
  • VOLTAGE-CONTROLLED DELAY LINE WITH REDUCED TIMING ERRORS AND JITTERS
    Publication number: 20040108872
    Abstract: A voltage controlled delay line having a plurality of delay cells is used to delay a first reference clock by a predetermined delay time to generate an in-phase first delay clock and to delay a second reference clock by the predetermined delay time to generate an in-phase second delay clock. Each delay cell has a first input port, a second input port, a first output port, and a second output port. The first output port of one delay cell and the second input port of another one delay cell having the same phase are electrically connected or the second output port of one delay cell and the first input port of another one delay cell having the same phase are electrically connected so that the first and second input port of each delay cell are not connected to the first and second output port of an adjacent delay cell.
    Type: Application
    Filed: June 10, 2003
    Publication date: June 10, 2004
    Inventors: Shen-Iuan Liu, Chih-Hao Sun, Hsiang-Hui Chang