Abstract: A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming a first gate structure around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a through via extending through isolation regions and into the substrate.

Abstract: A semiconductor device including a magnetic random access memory (MRAM) cell includes first and second magnetic random access memory (MRAM) cell structures disposed over a substrate. Each of the first and second MRAM cell structures includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, and a top electrode. The semiconductor device further includes a first insulating cover layer covering sidewalls of each of the first and second MRAM cell structures, and a second insulating cover layer disposed over the first insulating cover layer. The semiconductor device further includes a bottom dielectric layer filling a space between the first and second MRAM cell structures, and an upper dielectric layer disposed over the bottom dielectric layer. Each of the first insulating cover layer and the second insulating cover layer is discontinuous between the first MRAM cell structure and the second MRAM cell structure.

Abstract: A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming an opening in a semiconductor body, and the semiconductor body is p-type doped. The method also includes introducing n-type dopants into the semiconductor body to form a modified portion near the opening, and the modified portion is p-type doped. The method further includes forming a dielectric layer along the sidewalls and the bottom of the opening. In addition, the method includes forming a conductive structure over the dielectric layer to fill the opening.

Abstract: Semiconductor structures and fabrication processes are provided. A semiconductor according to the present disclosure includes a first region including a first fin, a second fin, and a third fin extending along a first direction, and a second region abutting the first region. The second region includes a fourth fin and a fifth fin extending along the first direction. The first fin is aligned with the fourth fin and the second fin is aligned with the fifth fin. The third fin terminates at an interface between the first region and the second region.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.

Abstract: Embodiments of the present disclosure provide methods of forming a RDL structure with a flat passivation surface. Some embodiments provide a stop layer for chemical mechanical polishing disposed under a passivation layer. Some embodiments provide an extra thickness of passivation deposition and a sacrificial passivation layer for passivation polishing. Some embodiments provide a modified RDL pattern by inserting dummy pattern objects to adjust pattern density.

Abstract: A first bond pad of a first device and a second bond pad of a second device are implanted with metal ions. The first and second semiconductor device are bonded together using a direct metal-to-metal bond and an overlay offset occurs between the bond pads such that a portion of the first bond pad and a portion of the second bond pad overlaps and contacts a dielectric material layer. During the bonding process, however, diffusion of the metal ions provides a barrier layer at the interface of the bond pads and the dielectric layers.

Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a conductive via passing through the first conductive layer and electrically connected to the first conductive layer. The chip structure includes a conductive pad over and in direct contact with the conductive via. The chip structure includes a second conductive layer over and spaced apart from the first conductive layer. The chip structure includes a first dielectric layer conformally covering a second lower portion of a sidewall of the second conductive layer. The chip structure includes a third conductive layer over the first dielectric layer.

Abstract: A redistribution structure is provided. A redistribution structure according to the present disclosure includes a first dielectric layer, a mesh metal feature disposed in the first dielectric layer and including a base portion and a frame portion surrounding the base portion, a second dielectric layer disposed over the first dielectric layer and the mesh metal feature, a redistribution feature disposed over the second dielectric layer, a passivation structure disposed over the redistribution feature and the second dielectric layer, a pad opening extending through the passivation structure to expose a top surface of the redistribution feature. The redistribution feature includes a plurality of contact vias that extend through the second dielectric layer to land on the frame portion of the mesh metal feature.

Abstract: An arrangement for supporting one or more bearings of a crankshaft assembly of a hydraulic fracturing pump includes a frame and one or more bearing supports. The frame is of a first material and defines one or more bearing support profiles. The bearing supports are of a second material different from the first material of the frame. The bearing supports are cast-in-place within the corresponding bearing support profiles of the frame and are configured to be in contact with an outer race of the corresponding bearings of the crankshaft assembly. Compared to the first material of the frame, the second material of the bearing supports is more effective at preventing slippage of the bearings.

Abstract: Through via structures and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a trench that extends through an insulation layer and into a substrate. The substrate has a first side (e.g., frontside) and a second side (e.g., backside). The insulation layer is disposed over the first side of the substrate. The method includes filling the trench with a dielectric material and performing a thinning process on the second side of the substrate that exposes the dielectric material. After the thinning process and removing the dielectric material from the trench, the method includes forming an electrically conductive structure (e.g., a barrier liner that wraps an electrically conductive plug) in the trench that extends through the substrate from the first side to the second side. A portion of the barrier liner that forms a top of the electrically conductive structure is disposed in the insulation layer.

Abstract: A first conductive pad disposed over a first side of a substrate in a first direction. A second conductive pad is disposed over a second side of the substrate in the first direction. A through-substrate via (TSV) extends into the substrate in the first direction. The TSV is disposed between the first conductive pad and the second conductive pad in the first direction. An air liner disposed between the TSV and the substrate in a second direction different from the first direction.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.

Abstract: A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.

Abstract: A pump assembly may include a bearing housing having a bore. The pump assembly may include a connecting rod connected to the bearing housing at a first end of the connecting rod and connected to a crosshead at a second end of the connecting rod via a wrist pin. The connecting rod may include a lubrication channel that extends within the connecting rod. The pump assembly may include a shell bearing in the bore of the bearing housing, the shell bearing having an inner surface and an outer surface. A portion of the inner surface of the shell bearing that contacts the crankshaft in a forward stroke of the crosshead may be uninterrupted by a groove or an aperture configured to direct lubrication fluid to the lubrication channel of the connecting rod.

Abstract: Embodiments of the present disclosure relate to methods for warpage correction. Particularly, embodiments of the present disclosure relate to substrate level warpage correction by depositing one or more warpage correction layers in a redistribution layer (RDL) structure, a front side warpage correction layer, and/or a back side warpage correction layer. In some embodiments, the warpage correction layer is a high stress dielectric layer. Characteristics of the warpage correction layer, such as stress level, and thickness, may be determined according to the substrate level warpage and the die level packaging scheme using an auto process control program.