Abstract: A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.

Abstract: A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.

Abstract: A thermal oxidation method for forming a gate dielectric layer for use within a field effect transistor device employs a thermal oxidizing atmosphere comprising a halogen getter material. By employing the halogen getter material, the field effect transistor device is formed with enhanced performance, in particular with respect to negative bias temperature instability lifetime.

Abstract: A thermal oxidation method for forming a gate dielectric layer for use within a field effect transistor device employs a thermal oxidizing atmosphere comprising a halogen getter material. By employing the halogen getter material, the field effect transistor device is formed with enhanced performance, in particular with respect to negative bias temperature instability lifetime.

Abstract: A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form the polysilicon patterns and an oxidizing step is performed. The mask layer is removed after the oxidizing step is performed.

Abstract: A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form the polysilicon patterns and an oxidizing step is performed. The mask layer is removed after the oxidizing step is performed.

Abstract: The present invention teaches the deposition of a pattern of interconnecting lines and bond pads. Passivation layers are deposited over this metal pattern. A layer of photosensitive polyimide is deposited over the passivation layers. This layer of photosensitive polyimide is patterned, exposed and developed to expose the underlying bonding pads. The remaining polyimide is cured and cross-linked and remains in place to serve as a buffer during further device packaging. Key to the present invention is that the remaining photosensitive polyimide is not removed after the bond pad has been exposed.

Abstract: A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide layer. The hard masking layer includes a full thickness portion and a thinner portion. The polysilicon layer below the full thickness portion is lightly doped forming a high resistance region. Below the thinner portion the polysilicon layer is heavily doped forming a low resistance region. However, in spite of the differences in resistance, the high resistance region and the low resistance region have the same thickness.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provided, containing a p-type region. An n-type photodiode region is formed within the p-type region. A field oxide isolation region is then formed which extends beyond the p-type region and also covers the p-type region except for an active region and an overlap part of the n-type photodiode region. An n-channel MOSFET is fabricated in the active region with one of the source/drain regions of the MOSFET extending over the overlap part of the n-type photodiode region. A blanket transparent insulating layer is then deposited.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: A method for preventing gate oxide damage caused by post poly definition implantation is disclosed. It is shown that the antenna ratio that is correlatable to oxide damage can be reduced and made to approach zero by implementing a mask layout during ion implantation. This involves covering all of the polysilicon electrodes with a photoresist mask, and reducing the effective antenna ratio to zero, and performing ion implantation to form source/drain regions thereafter. In this manner, the dependency of ion implantation to pattern sensitivity is also removed.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: A method for preventing gate oxide damage caused by post poly definition implantation is disclosed. It is shown that the antenna ratio that is correlatable to oxide damage can be reduced and made to approach zero by implementing a mask layout during ion implantation. This involves covering all of the polysilicon electrodes with a photoresist mask, and reducing the effective antenna ratio to zero, and performing ion implantation to form source/drain regions thereafter. In this manner, the dependency of ion implantation to pattern sensitivity is also removed.

Abstract: A method is provided for forming a plurality of structures with different resistance values in a single polysilicon film as follows. Form a polysilicon layer upon a substrate. Pattern the polysilicon to expose a portion thereof which is to be reduced in thickness. Partially etch through the polysilicon to produce a reduced thickness thereof while leaving the remainder of the polysilicon with the original thickness. Dope the polysilicon layer through the polysilicon with variable doping as a function of the reduced thickness and the original thickness of the polysilicon.

Abstract: Device layouts are described which increase the photon current of a metal oxide semiconductor image sensor. The metal oxide semiconductor can be NMOS, PMOS, or CMOS. The key part of the photon current of the image sensors comes from the depletion region at the PN junction between the drain region and the substrate material. The layouts used significantly increase the area of this depletion region illuminated by a stream of photons. The layouts have a drain region which takes the shape of a number of parallel fingers perpendicular to the gate electrode, a number of parallel fingers parallel to the gate electrode, or a spiral. The drain regions of these layouts significantly increase the area of the drain depletion region illuminated by a stream of electrons.

Abstract: This method forms structures with different resistance values from a single polysilicon film formed on a substrate. Form a hard masking layer on the polysilicon film. Form a photoresist mask over the hard masking layer. Partially etch the hard masking layer through the photoresist mask to reduce the thickness of the polysilicon while leaving the remainder of the hard masking layer with the original thickness. The thickness is reduced in locations where a low resistance is to be located in the polysilicon film. Then dope the polysilicon layer through the hard masking layer with variable doping as a function of the reduced thickness and the original thickness of the hard masking layer.

Abstract: A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

Abstract: A wafer edge seal ring structure is disclosed to provide reduced particulate contaminant generation during wafer processing of high density integrated circuits. The structure is formed by delimiting the deposition of layers at the peripheral edges of wafers. It is shown that as each layer is deposited and then essentially trimmed back from the edge of the wafer through a judicious use of mask and etching, and/or edge-bead rinsing (EBR) and later sealed by wafer edge exposure (WEE), the otherwise present abnormal growth of layers are prevented from building up into protrusions at the edge of wafer that later peel or break up to form particulate matter and fine dust. The method, which is also disclosed, teaches how each layer is recessed at appropriate distances from the wafer edge and how the whole ring structure is sealed against attacking particles.

Abstract: The present invention provides a method for removing unwanted coating layer at wafer edge by first immersing the wafer edge in a cleaning solution and then immersing in a rinsing solution such as deionized water to remove the residual cleaning solution from the surface of the wafer. The wafer can be dried in a subsequent spin dry process.