Abstract: The invention relates to a layout method for a transistor with improved ESD robustness. The layout method includes defining a ring region from a first conductive type; defining a first and a second rectangular diffusion regions from a second conductive type, wherein the first and second rectangular diffusion regions are isolated from each other; defining a ring diffusion region of the second conductive type between the first and second rectangular diffusion regions; defining a first gate electrode between the first rectangular diffusion region of the second conductive type and the ring diffusion region of the second conductive region; and defining a second gate electrode between the second rectangular diffusion region of the second conductive type and the ring diffusion region of the second conductive type.