Abstract: One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region.

Abstract: The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective coating layer and a capping layer. The bottom electrode is on the substrate. The capacitor dielectric layer is on the bottom electrode. The capacitor dielectric layer has a first region and a second region adjacent to the first region. The top electrode is on the first region of the capacitor dielectric layer. The etching stop layer is on the top electrode. The first anti-reflective coating layer is on the etching stop layer, in which the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall. The capping layer overlies the sidewall, the etching stop layer, the second region of the capacitor dielectric layer, in which the capping layer is formed from oxide or nitride.

Abstract: A metal-insulator-metal (MIM) capacitor structure and method for forming MIM capacitor structure are provided. The MIM capacitor structure includes a substrate and a metal-insulator-metal (MIM) capacitor formed on the substrate. The MIM capacitor includes a capacitor top metal (CTM) layer, a capacitor bottom metal (CBM) layer and an insulator formed between the CTM layer and the CBM layer. The insulator includes an insulating layer and a first high-k dielectric layer, and the insulating layer includes a nitride layer and an oxide layer, and the nitride layer is formed between the first high-k dielectric layer and the oxide layer.

Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.

Abstract: A system and method for blocking light from regions around a photodiode in a pixel of an image sensor is provided. In an embodiment a first optical block layer is formed on a first glue layer and a second glue layer is formed on the first optical block layer. The formation of the first optical block layer and the second glue layer is repeated one or more times to form multiple optical block layers and multiple glue layers. As such, if voids open up in the optical block layers during further processing, there is another optical block layer to block any light that may have penetrated through the void.

Abstract: Embodiments of mechanisms for forming a metal-insulator-metal (MIM) capacitor structure are provided. The metal-insulator-metal capacitor structure includes a substrate. The MIM capacitor structure also includes a CBM layer formed on the substrate, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer. The MIM capacitor structure further includes a first high-k dielectric layer formed on the CBM layer, an insulating layer formed on the first high-k dielectric layer and a second high-k dielectric layer formed on the insulating layer. The MIM capacitor structure also includes a CTM layer formed on the second high-k dielectric layer, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer.

Abstract: The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective coating layer and a capping layer. The bottom electrode is on the substrate. The capacitor dielectric layer is on the bottom electrode. The capacitor dielectric layer has a first region and a second region adjacent to the first region. The top electrode is on the first region of the capacitor dielectric layer. The etching stop layer is on the top electrode. The first anti-reflective coating layer is on the etching stop layer, in which the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall. The capping layer overlies the sidewall, the etching stop layer, the second region of the capacitor dielectric layer, in which the capping layer is formed from oxide or nitride.

Abstract: Embodiments of mechanisms of a backside illuminated image sensor device structure are provided. The backside illuminated image sensor device structure includes a substrate having a frontside and a backside and a pixel array formed in the frontside of the substrate. The backside illuminated image sensor device structure further includes an antireflective layer formed over the backside of the substrate, and the antireflective layer is made of silicon carbide nitride.

Abstract: Embodiments of mechanisms for forming a metal-insulator-metal (MIM) capacitor structure are provided. The metal-insulator-metal capacitor structure includes a substrate. The MIM capacitor structure also includes a CBM layer formed on the substrate, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer. The MIM capacitor structure further includes a first high-k dielectric layer formed on the CBM layer, an insulating layer formed on the first high-k dielectric layer and a second high-k dielectric layer formed on the insulating layer. The MIM capacitor structure also includes a CTM layer formed on the second high-k dielectric layer, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer.

Abstract: A metal-insulator-metal (MIM) capacitor structure and method for forming MIM capacitor structure are provided. The MIM capacitor structure includes a substrate and a metal-insulator-metal (MIM) capacitor formed on the substrate. The MIM capacitor includes a capacitor top metal (CTM) layer, a capacitor bottom metal (CBM) layer and an insulator formed between the CTM layer and the CBM layer. The insulator includes an insulating layer and a first high-k dielectric layer, and the insulating layer includes a nitride layer and an oxide layer, and the nitride layer is formed between the first high-k dielectric layer and the oxide layer.

Abstract: One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region.

Abstract: Embodiments of mechanisms of a backside illuminated image sensor device structure are provided. The backside illuminated image sensor device structure includes a substrate having a frontside and a backside and a pixel array formed in the frontside of the substrate. The backside illuminated image sensor device structure further includes an antireflective layer formed over the backside of the substrate, and the antireflective layer is made of silicon carbide nitride.

Abstract: A system and method for blocking light from regions around a photodiode in a pixel of an image sensor is provided. In an embodiment a first optical block layer is formed on a first glue layer and a second glue layer is formed on the first optical block layer. The formation of the first optical block layer and the second glue layer is repeated one or more times to form multiple optical block layers and multiple glue layers. As such, if voids open up in the optical block layers during further processing, there is another optical block layer to block any light that may have penetrated through the void.

Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.

Abstract: A thermal acupuncture and moxibustion device is disclosed. A dosage detection unit decodes and analyzes signals from a temperature sensor. A buffering amplifier amplifies signals from the dosage detection unit. An analog/digital converting unit converts the amplified signals into digital signals. A microcomputer operation unit determines a desired dosage from the digital signals based on a dosage control software, and sends out pulse signals representing the desired dosage. A thermal acupuncture and moxibustion digital/analog signal amplifier converts the pulse signals into analog signals and amplifies the same. A thermal acupuncture and moxibustion driving unit drives a heating wire so as to adjust the temperature of the thermal acupuncture and moxibustion unit.