Patents by Inventor Chih-Hong Chuang
Chih-Hong Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072411Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicant: Pegatron CorporationInventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Chih-Wei Liao, Chia-Hung Chen, Chen-Kuang Wang, Wen-Hgin Chuang, Chia-Hong Chen, Hsi Yung Chen
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Patent number: 10123413Abstract: A temporary package substrate includes a first copper layer, a second copper layer, a third copper layer, a first plating copper layer, a second plating copper layer, a third plating copper layer, a first dielectric layer, a second dielectric layer and two circuit structures. The second copper layer is located between the first and the third copper layers, and edges of the second copper layer are retracted a distance compared to edges of the first copper layer and edges of the third copper layer. The first and the second dielectric layers completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer. Each of the circuit structures includes at least two patterned circuit layers, an insulation layer located between the patterned circuit layers, and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers.Type: GrantFiled: May 15, 2017Date of Patent: November 6, 2018Assignee: Subtron Technology Co., Ltd.Inventors: Chih-Hong Chuang, Chien-Hung Wu
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Publication number: 20170251552Abstract: A temporary package substrate includes a first copper layer, a second copper layer, a third copper layer, a first plating copper layer, a second plating copper layer, a third plating copper layer, a first dielectric layer, a second dielectric layer and two circuit structures. The second copper layer is located between the first and the third copper layers, and edges of the second copper layer are retracted a distance compared to edges of the first copper layer and edges of the third copper layer. The first and the second dielectric layers completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer. Each of the circuit structures includes at least two patterned circuit layers, an insulation layer located between the patterned circuit layers, and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Applicant: Subtron Technology Co., Ltd.Inventors: Chih-Hong Chuang, Chien-Hung Wu
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Patent number: 9693468Abstract: A method of manufacturing a package substrate is provided. A first copper layer and a first plating copper layer formed thereon, a first dielectric layer, a second copper layer and a second plating copper layer formed thereon, a second dielectric layer, a third copper layer and a third plating copper layer formed thereon are provided and laminated, so that the first and the second dielectric layers encapsulate edges of the second copper layer and the second plating copper layer to form a temporary carrier. Two circuit structures are formed on two opposite surfaces of the temporary carrier. The temporary carrier and the circuit structures are cut to expose the edges of the second copper layer and the second plating copper layer, and separated along the exposed edges of the second copper layer and the second plating copper layer to form two package substrates independent from each other.Type: GrantFiled: September 7, 2015Date of Patent: June 27, 2017Assignee: Subtron Technology Co., Ltd.Inventors: Chih-Hong Chuang, Chien-Hung Wu
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Patent number: 9603263Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. At least a through hole passing through the sealed area is formed. Two insulating layers are formed on the two metal layers. Two conductive layers are formed on the two insulating layers. The two insulating layers and the two conductive layers are laminated to the two metal layers bonded to each other, wherein the metal layers are embedded between the two insulating layers, and the two insulating layers fill into the through hole. The sealed area of the two metal layers is separated to form two separated circuit substrates. Therefore, the thinner substrate can be operated in the following steps, such as patterning process or plating process. In addition, the method may be extended to manufacture the circuit substrate with odd-numbered layer or even-numbered layer.Type: GrantFiled: July 19, 2012Date of Patent: March 21, 2017Assignee: Subtron Technology Co., Ltd.Inventors: Chih-Hong Chuang, Tzu-Wei Huang
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Publication number: 20170006713Abstract: A method of manufacturing a package substrate is provided. A first copper layer and a first plating copper layer formed thereon, a first dielectric layer, a second copper layer and a second plating copper layer formed thereon, a second dielectric layer, a third copper layer and a third plating copper layer formed thereon are provided and laminated, so that the first and the second dielectric layers encapsulate edges of the second copper layer and the second plating copper layer to form a temporary carrier. Two circuit structures are formed on two opposite surfaces of the temporary carrier. The temporary carrier and the circuit structures are cut to expose the edges of the second copper layer and the second plating copper layer, and separated along the exposed edges of the second copper layer and the second plating copper layer to form two package substrates independent from each other.Type: ApplicationFiled: September 7, 2015Publication date: January 5, 2017Inventors: Chih-Hong Chuang, Chien-Hung Wu
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Publication number: 20150136364Abstract: A heat dissipation device includes a package carrier, heat dissipating fins, an atomizer and a driving unit. The package carrier has a carrying surface and a disposing surface divided into a first region and a second region. The heat dissipating fines are located in the second region and define an accommodating space with the package carrier. An extending direction of the heat dissipating fines is perpendicular to an extending direction of the package carrier. The atomizer is disposed on the heat dissipating fines and located in the accommodating space. The atomizer includes an atomization unit, a liquid containing cavity and a fluid channel. The liquid containing cavity, the heat dissipating fines and the package carrier define a fluid chamber. The driving unit is electrically connected to the atomizer so as to drive a working fluid to the atomization unit and atomize the working fluid into an atomization micro-mist.Type: ApplicationFiled: January 13, 2014Publication date: May 21, 2015Applicant: SUBTRON TECHNOLOGY CO., LTD.Inventor: Chih-Hong Chuang
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Patent number: 8563363Abstract: A fabricating method of a semiconductor package structure is provided. A dielectric layer having a first surface and a second surface is provided. A patterned metal layer has been formed on the first surface of the dielectric layer. An opening going through the first and the second surfaces is formed. A carrier having a third surface and a fourth surface is formed at the second surface. A portion of the third surface is exposed by the opening of the dielectric layer. A semiconductor die having a joining surface and a side-surface is joined in the opening. At least a through hole going through the third and the fourth surfaces is formed. A metal layer having at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity is formed on the fourth surface.Type: GrantFiled: August 21, 2012Date of Patent: October 22, 2013Assignee: Subtron Technology Co., Ltd.Inventors: Tzyy-Jang Tseng, Chin-Sheng Wang, Chih-Hong Chuang
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Patent number: 8510936Abstract: A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer.Type: GrantFiled: March 17, 2010Date of Patent: August 20, 2013Assignee: Subtron Technology Co., Ltd.Inventors: Chih-Hong Chuang, Tzu-Wei Huang
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Patent number: 8390013Abstract: A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity.Type: GrantFiled: October 29, 2010Date of Patent: March 5, 2013Assignee: Subtron Technology Co., Ltd.Inventors: Tzyy-Jang Tseng, Chin-Sheng Wang, Chih-Hong Chuang
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Publication number: 20130011971Abstract: A fabricating method of a semiconductor package structure is provided. A dielectric layer having a first surface and a second surface is provided. A patterned metal layer has been formed on the first surface of the dielectric layer. An opening going through the first and the second surfaces is formed. A carrier having a third surface and a fourth surface is formed at the second surface. A portion of the third surface is exposed by the opening of the dielectric layer. A semiconductor die having a joining surface and a side-surface is joined in the opening. At least a through hole going through the third and the fourth surfaces is formed. A metal layer having at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity is formed on the fourth surface.Type: ApplicationFiled: August 21, 2012Publication date: January 10, 2013Applicant: Subtron Technology Co., Ltd.Inventors: TZYY-JANG TSENG, Chin-Sheng Wang, Chih-Hong Chuang
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Publication number: 20120279630Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. At least a through hole passing through the sealed area is formed. Two insulating layers are formed on the two metal layers. Two conductive layers are formed on the two insulating layers. The two insulating layers and the two conductive layers are laminated to the two metal layers bonded to each other, wherein the metal layers are embedded between the two insulating layers, and the two insulating layers fill into the through hole. The sealed area of the two metal layers is separated to form two separated circuit substrates. Therefore, the thinner substrate can be operated in the following steps, such as patterning process or plating process. In addition, the method may be extended to manufacture the circuit substrate with odd-numbered layer or even-numbered layer.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Applicant: SUBTRON TECHNOLOGY CO. LTD.Inventors: Chih-Hong Chuang, Tzu-Wei Huang
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Publication number: 20120181066Abstract: A package carrier is suitable for carrying a heat-generating element. The package carrier includes a substrate, an insulating structure with high thermal conductivity, and a patterned conductive layer. The substrate has a surface. The insulating structure with high thermal conductivity is configured on a portion of the surface of the substrate. The patterned conductive layer is configured on a portion of the surface of substrate, and a portion of the patterned conductive layer covers the insulating structure with high thermal conductivity. The heat-generating element is suitable for being configured on the portion of the patterned conductive layer which is located on the insulating structure with high thermal conductivity. A coefficient of thermal expansion (CTE) of the insulating structure with high thermal conductivity is between a CTE of the substrate and a CTE of the heat-generating element.Type: ApplicationFiled: March 1, 2011Publication date: July 19, 2012Applicant: SUBTRON TECHNOLOGY CO. LTD.Inventor: Chih-Hong Chuang
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Publication number: 20120088117Abstract: A substrate structure including a first metal substrate, a second metal substrate, a frame fixture, a first conductive layer, a second conductive layer, a first adhesive layer and a second adhesive layer is provided. The second metal substrate is stacked over the first metal substrate. The frame fixture is disposed around the first metal substrate and the second metal substrate. The first adhesive layer is disposed between the first conductive layer and the first metal substrate, and between the first conductive layer and the frame fixture. The first conductive layer is fixed on an upper surface of the frame fixture by the first adhesive layer. The second adhesive layer is disposed between the second conductive layer and the second metal substrate, and between the second conductive layer and the frame fixture. The second conductive layer is fixed on a lower surface of the frame fixture by the second adhesive layer.Type: ApplicationFiled: November 29, 2010Publication date: April 12, 2012Applicant: Subtron Technology Co., Ltd.Inventor: Chih-Hong Chuang
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Publication number: 20120007252Abstract: A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity.Type: ApplicationFiled: October 29, 2010Publication date: January 12, 2012Applicant: Subtron Technology Co. Ltd.Inventors: TZYY-JANG TSENG, Chin-Sheng Wang, Chih-Hong Chuang
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Publication number: 20110154657Abstract: A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer.Type: ApplicationFiled: March 17, 2010Publication date: June 30, 2011Applicant: SUBTRON TECHNOLOGY CO. LTD.Inventors: Chih-Hong Chuang, Tzu-Wei Huang
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Publication number: 20110154658Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. At least a through hole passing through the sealed area is formed. Two insulating layers are formed on the two metal layers. Two conductive layers are formed on the two insulating layers. The two insulating layers and the two conductive layers are laminated to the two metal layers bonded to each other, wherein the metal layers are embedded between the two insulating layers, and the two insulating layers fill into the through hole. The sealed area of the two metal layers is separated to form two separated circuit substrates. Therefore, the thinner substrate can be operated in the following steps, such as patterning process or plating process. In addition, the method may be extended to manufacture the circuit substrate with odd-numbered layer or even-numbered layer.Type: ApplicationFiled: December 28, 2010Publication date: June 30, 2011Applicant: SUBTRON TECHNOLOGY CO. LTD.Inventors: Chih-Hong Chuang, Tzu-Wei Huang