Abstract: A dynamic feed-forward OPAMP-based circuit is provided. A first amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. A second amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is coupled to a non-inverting input terminal of the first amplifying stage. A second capacitor is coupled to an inverting input terminal of the first amplifying stage. A feed-forward transconductance stage is coupled between the first and second capacitors and the second amplifying stage. The first and second capacitors and the feed-forward stage form a high-frequency path with a first gain curve, and the first amplifying stage and the second amplifying stage form a high-gain path with a second gain curve. The operational amplifier provides an open-loop gain according to the first and second gain curves.

Abstract: A low pass filter includes a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential operational amplifier, wherein the first amplifier stage is arranged to process a differential input signal to generate a differential intermediate signal, the differential input signal having a first input signal and a second input signal, and the differential intermediate signal having a first intermediate signal and a second intermediate signal. The second amplifier stage has no common-mode feedback and is arranged to process the differential intermediate signal to generate a differential output signal, wherein the differential output signal has a first output signal corresponding to the first input signal and a second output signal corresponding to the second input signal. Since the noisy common-mode feedback is removed from the second amplifier stage, the overall common-mode noise of the low pass filter can be decreased.

Abstract: A current controlling device includes: a first resistive circuit arranged to selectively conduct a first current to a first output terminal from a first input terminal; and a second resistive circuit arranged to selectively conduct a second current to a second output terminal from the first input terminal; wherein when the first resistive circuit conducts the first current to the first output terminal and when the second resistive circuit does not conduct the second current to the second output terminal, the first input terminal has a first input impedance; when the first resistive circuit does not conduct the first current to the first output terminal and when the second resistive circuit conducts the second current to the second output terminal, the first input terminal has a second input impedance substantially equal to the first input impedance.

Abstract: An analog-to-digital converting device includes: an integrator arranged to generate an integrating signal according to an analog input signal and a first analog feedback signal; a low-pass filter arranged to generate a first filtered signal according to the integrating signal; an analog-to-digital converter arranged to generate a digital output signal according to the first filtered signal; and a first digital-to-analog converter arranged to generate the first analog feedback signal according to the digital output signal.

Abstract: A dynamic feed-forward OPAMP-based circuit is provided. A first amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. A second amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is coupled to a non-inverting input terminal of the first amplifying stage. A second capacitor is coupled to an inverting input terminal of the first amplifying stage. A feed-forward transconductance stage is coupled between the first and second capacitors and the second amplifying stage. The first and second capacitors and the feed-forward stage form a high-frequency path with a first gain curve, and the first amplifying stage and the second amplifying stage form a high-gain path with a second gain curve. The operational amplifier provides an open-loop gain according to the first and second gain curves.

Abstract: A multi-mode OPAMP-based circuit is provided. An input amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. An output amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is disposed in a first negative feedback loop of the output amplifying stage. A second capacitor is disposed in a second negative feedback loop of the output amplifying stage. A third capacitor is selectively disposed in a first positive feedback loop of the output amplifying stage or coupled to the first capacitor in parallel according to a control signal. A fourth capacitor is selectively disposed in a second positive feedback loop of the output amplifying stage or coupled to the second capacitor in parallel according to the control signal.

Abstract: A microphone bias circuit is disclosed. A current source provides a first current. A voltage buffer provides a first reference voltage. A microphone coupled between the current source and the first reference voltage receives acoustic waves and converts the received acoustic waves to a second current. A loading device coupled between the current source and a second reference voltage lower than the first reference voltage outputs an output voltage according to the first current and the second current.

Abstract: A code mapping method includes: providing M bits of digital input codes; checking the 1st bit of the M bits to generate a checking result; determining whether to perform 2's compliment operation on the 2nd to Mth bits according to the checking result; and converting the 1st to Nth bits of the M bits into P bits according to a designated mapping manner.

Abstract: A digital-to-analog converter includes an operational amplifying circuit, a switched capacitor circuit, an R-string sub-circuit, and a direct-charge transfer circuit. The operational amplifying circuit has a pair of differential input ends and a pair of differential output ends. The switched capacitor circuit is coupled to the pair of differential input ends of the operational amplifying circuit. The R-string sub-circuit is coupled to the switched capacitor circuit and the pair of differential input ends of the operational amplifying circuit. The direct-charge transfer circuit is coupled to the pair of differential input ends and the pair of differential output ends of the operational amplifying circuit.

Abstract: A digital-to-analog converter includes an operational amplifying circuit, a switched capacitor circuit, an R-string sub-circuit, and a direct-charge transfer circuit. The operational amplifying circuit has a pair of differential input ends and a pair of differential output ends. The switched capacitor circuit is coupled to the pair of differential input ends of the operational amplifying circuit. The R-string sub-circuit is coupled to the switched capacitor circuit and the pair of differential input ends of the operational amplifying circuit. The direct-charge transfer circuit is coupled to the pair of differential input ends and the pair of differential output ends of the operational amplifying circuit.

Abstract: A segmented digital-to-analog converter (DAC) is disclosed. In the present invention, the segmented DAC of the present invention comprises a signal component processing stage and a plurality of noise component processing stages cascaded with the signal component processing stage. A noise component of an input word for the DAC is split into a plurality of portions to be processed. By doing so, effect due to gain mismatch(es) in an analog portion of the DAC can be effectively reduced without significantly increasing DAC cells used in the DAC.

Abstract: A segmented digital-to-analog converter (DAC) is disclosed. In the present invention, the segmented DAC of the present invention comprises a signal component processing stage and a plurality of noise component processing stages cascaded with the signal component processing stage. A noise component of an input word for the DAC is split into a plurality of portions to be processed.

Abstract: A power supply. The power supply provides power to a real-time clock generator when system power is not available and comprises first and second regulators, an energy storage device, and a switch. The first regulator receives a system power and generates a first regulated voltage when the system power is available. The energy storage device is coupled to a node. The second regulator comprises an input coupled to the node and provides a second regulated voltage to a real-time clock generator. The switch is coupled between the first regulator and the node. The switch is turned on when the system power is available and turned off when the system power is not available.

Abstract: A voltage regulator includes an undervoltage detector having a charge transistor smaller than an output transistor of the voltage regulator, providing a detection path for fast response, compensating undervoltage without large control current when loading changes from light to heavy.

Abstract: A voltage regulator with a local feedback loop is disclosed, which provides adaptive control currents responsive to load transient to regulate abrupt voltage variations. The voltage regulator has an amplifier having a first input coupled to a reference voltage, a second input coupled to a feedback signal, and an output producing a first control signal; an output transistor having a control input, a first electrode coupled to a supplied voltage, and a second electrode coupled to an output terminal to output a regulated output voltage; a feedback circuit coupled to the output terminal to produce the feedback signal; and an adaptive biasing device coupled to the output terminal and the control input of the output transistor, for outputting control currents responsive to variations in the regulated output voltage to drive the output transistor to compensate the variations.

Abstract: A voltage regulator includes an undervoltage detector having a charge transistor smaller than an output transistor of the voltage regulator, providing a detection path for fast response, compensating undervoltage without large control current when loading changes from light to heavy.

Abstract: A microphone bias circuit is disclosed. A current source provides a first current. A voltage buffer provides a first reference voltage. A microphone coupled between the current source and the first reference voltage receives acoustic waves and converts the received acoustic waves to a second current. A loading device coupled between the current source and a second reference voltage lower than the first reference voltage outputs an output voltage according to the first current and the second current.

Abstract: A voltage regulator including a transconductance amplifying unit, a transresistance amplifying unit, a feedback unit, a differential amplifying unit, and a compensation capacitor. The transconductance amplifying unit includes two inputs for receiving a feedback voltage and a reference voltage, and includes an output for outputting a current. The transresistance amplifying unit includes an input for receiving the current, and transforming the current into an output voltage. The feedback unit generates the feedback voltage with reference to the output voltage. The differential amplifying unit includes two inputs for receiving the feedback voltage and the reference voltage, and includes an output for outputting a differential voltage. The compensation capacitor is coupled between the output of the differential amplifying unit and the input of the transresistance amplifying unit.

Abstract: A voltage regulating circuit for providing a regulated output voltage. The voltage regulating circuit includes a voltage regulator, a converting circuit, a capacitive device, a first current mirror module, and a second current mirror module. The voltage regulator has a first output producing the regulated output voltage and a second output producing a pass voltage. The converting circuit converts the pass voltage into a first current and a second current passing through a first converting node and a second converting node respectively, where the first current charges/discharges the capacitive device. The first current mirror module has a first current mirror path coupled to the first converting node and a second current mirror path coupled to the second converting node. The second current mirror module has a first current mirror path coupled to the second converting node and a second current mirror path coupled to the first output.

Abstract: A voltage regulating circuit for providing a regulated output voltage. The voltage regulating circuit includes a voltage regulator, a converting circuit, a capacitive device, a first current mirror module, and a second current mirror module. The voltage regulator has a first output producing the regulated output voltage and a second output producing a pass voltage. The converting circuit converts the pass voltage into a first current and a second current passing through a first converting node and a second converting node respectively, where the first current charges/discharges the capacitive device. The first current mirror module has a first current mirror path coupled to the first converting node and a second current mirror path coupled to the second converting node. The second current mirror module has a first current mirror path coupled to the second converting node and a second current mirror path coupled to the first output.