Abstract: A method of manufacturing an integrated circuit (IC) device includes forming, in a circuit region, active regions elongated along a first axis, and gate regions over the active regions and elongated along a second axis. The method further includes depositing a lower metal layer over the circuit region, patterning the lower metal layer to form lower conductive patterns elongated along the first axis, depositing an upper metal layer over the lower metal layer, and patterning the upper metal layer to form upper conductive patterns elongated along the second axis and first lateral upper conductive pattern. The upper conductive patterns include at least one input or output configured to electrically couple the circuit region to external circuitry. The first lateral upper conductive pattern is contiguous with and projects, along the first axis, from a first upper conductive pattern, and is over and electrically coupled to a first lower conductive pattern.

Abstract: An electronic device, including a metal back cover, a ground radiator, a third radiator, and a metal frame including a first cutting opening, a second cutting opening, a first radiator located between the first cutting opening and the second cutting opening, and a second radiator located beside the second cutting opening and separated from the first radiator by the second cutting opening, is provided. An end of a first slot formed between the metal back cover and a first part of the first radiator is communicated with the first cutting opening, and a second slot formed between the metal back cover and a second part of the first radiator and between the metal back cover and the second radiator is communicated with the second cutting opening. The ground radiator connects the metal back cover and the first radiator and separates the first slot from the second slot.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.

Abstract: A SAR ADC includes: a sample-hold (S/H) circuit sampling an input voltage to generate a S/H output signal; a DAC generating a DAC output signal; a comparator comparing the DAC output signal with the S/H output signal to generate a comparison output signal; a SAR combinational digital circuit group; a multiplexer circuit; and a plurality of registers for registering the comparison output signal as register output signals and outputting as an output signal of the SAR ADC. The SAR combinational digital circuit group generates a plurality of first and second SAR output signals based on the register output signals. The multiplexer circuit is controlled by on the register output signals to select among the first and the second SAR output signals as a plurality of multiplexer output signals for sending to the DAC. A capacitor coupling relationship of the DAC is controlled by the multiplexer output signals.

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

Abstract: Disclosed is a high-voltage device with ESD robustness. The high-voltage device is formed on a surface of a semiconductor substrate of a first type. A deep well of a second type opposite to the first type is formed on the surface. A filed isolation layer on the surface separates a drain active region from a source active region, and a control gate on top of the field isolation layer serves as a gate electrode of the high-voltage device. A first well of the second type at least partially overlaps the source active region, extends below the field isolation layer and at least partially overlaps the control gate. A buried layer of the first type at a bottom of the deep well has an extensive portion below the control gate. The deep well provides a conductive channel allowing current to flow from the drain active region to the source active region.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A power backup circuit provides a plurality of input power sources to back up a load. The power backup circuit includes a first switch, a second switch, and a control unit. The input power sources at least includes a first input power source and a second input power source. If the input power source of the load needs to be changed from the first input power source to the second input power source, the control unit controls the first switch to be coupled to the second input power source and controls the second switch to be coupled to the second input power source after the control unit effects a supply current flowing through a first power supply path and a second power supply path both coupled to the first input power source and the load to be reduced below a current threshold.

Abstract: A power backup circuit provides a plurality of input power sources to back up a load. The power backup circuit includes a first switch, a second switch, and a control unit. The input power sources at least includes a first input power source and a second input power source. If the input power source of the load needs to be changed from the first input power source to the second input power source, the control unit controls the first switch to be coupled to the second input power source and controls the second switch to be coupled to the second input power source after the control unit effects a supply current flowing through a first power supply path and a second power supply path both coupled to the first input power source and the load to be reduced below a current threshold.

Abstract: A power supply system includes a plurality of power supply units and a plurality of battery units. Each power supply unit is coupled to a common bus through a first switch. Each battery unit is corresponding to each power supply unit, and is coupled to the common bus through a second switch. Any one of the power supply units turns on the corresponding first switch and turns on the second switches of other battery units so that the power supply unit acquires power electricity from other battery units through the common bus.

Abstract: A power supply device includes a PF correction circuit, a power switching circuit and a control circuit. The PF correction circuit converts an input voltage to a bus voltage according to a control signal to supply a later stage circuit. The power switching circuit selectively switches to conduct a first source or a second source to the PF correction circuit to provide the input voltage to the PF correction circuit. The control circuit outputs the control signal to the PF correction circuit. When the control circuit detects a first voltage of the first source connecting to the PF correction circuit is abnormal, the control circuit determines whether a second voltage of the second source is smaller than the bus voltage and controls the power switching circuit to switch when the second voltage is smaller than the bus voltage to conduct the second source to the PF correction circuit.

Abstract: A power supply device includes a PF correction circuit, a power switching circuit and a control circuit. The PF correction circuit converts an input voltage to a bus voltage according to a control signal to supply a later stage circuit. The power switching circuit selectively switches to conduct a first source or a second source to the PF correction circuit to provide the input voltage to the PF correction circuit. The control circuit outputs the control signal to the PF correction circuit. When the control circuit detects a first voltage of the first source connecting to the PF correction circuit is abnormal, the control circuit determines whether a second voltage of the second source is smaller than the bus voltage and controls the power switching circuit to switch when the second voltage is smaller than the bus voltage to conduct the second source to the PF correction circuit.

Abstract: A fabricating method of a recess with asymmetric walls includes the steps of providing a substrate comprising a top surface. A recess is formed in the substrate, wherein the recess comprises a first wall, a second wall and a bottom. A patterned mask is formed to cover the substrate. Part of the top surface adjacent to the second wall is exposed through the patterned mask. Finally, the substrate is removed to form a sloping wall, wherein the sloping wall, the first wall and the bottom form a recess with asymmetric walls.

Abstract: A fabricating method of a recess with asymmetric walls includes the steps of providing a substrate comprising a top surface. A recess is formed in the substrate, wherein the recess comprises a first wall, a second wall and a bottom. A patterned mask is formed to cover the substrate. Part of the top surface adjacent to the second wall is exposed through the patterned mask. Finally, the substrate is removed to form a sloping wall, wherein the sloping wall, the first wall and the bottom form a recess with asymmetric walls.