Patents by Inventor Chih-Hsiang Chu

Chih-Hsiang Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FeRAM MFM STRUCTURE WITH SELECTIVE ELECTRODE ETCH
    Publication number: 20250048647
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Chih-Hsiang Chang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Tzu-Yu Chen, Fu-Chen Chang
  • Fin-type field effect transistor structure and manufacturing method thereof
    Patent number: 9899526
    Abstract: A fin-type field effect transistor comprising a substrate, fins, insulators, at least one gate stack and strained material portions is described. The insulators are disposed in trenches of the substrate and between the fins. The upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile. The at least one gate stack is disposed over the fins and on the insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Wei Chiu, Li-Te Hsu, Chung-Fan Huang, Chih-Hsiang Chu
  • FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170207338
    Abstract: A fin-type field effect transistor comprising a substrate, fins, insulators, at least one gate stack and strained material portions is described. The insulators are disposed in trenches of the substrate and between the fins. The upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile. The at least one gate stack is disposed over the fins and on the insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Yi-Wei Chiu, Li-Te Hsu, Chung-Fan Huang, Chih-Hsiang Chu