Abstract: A system for model protection includes a processor. The processor is arranged to execute a guest virtual machine (VM), a primary VM, and a hypervisor. The guest VM includes a model, and is arranged to send at least one command to a command hub. The primary VM is arranged to refer to the at least one command sent from the command hub to manage and configure a protection setting for a protected model derived from the model. The hypervisor is arranged to receive a safety setting command sent by the primary VM, and manage and configure the safety protection component according to the safety setting command, to set a read-only mode of the protected model.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: A fin-type field effect transistor comprising a substrate, fins, insulators, at least one gate stack and strained material portions is described. The insulators are disposed in trenches of the substrate and between the fins. The upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile. The at least one gate stack is disposed over the fins and on the insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

Abstract: A fin-type field effect transistor comprising a substrate, fins, insulators, at least one gate stack and strained material portions is described. The insulators are disposed in trenches of the substrate and between the fins. The upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile. The at least one gate stack is disposed over the fins and on the insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.