Patents by Inventor CHIH-HSIANG FAN

CHIH-HSIANG FAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961768
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20230282482
    Abstract: A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.
    Type: Application
    Filed: June 4, 2022
    Publication date: September 7, 2023
    Inventors: Tsung-Han Shen, Kevin Chang, Yu-Ming Li, Chih-Hsiang Fan, Yi-Ting Wang, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
  • Publication number: 20230274983
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Publication number: 20230231037
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.
    Type: Application
    Filed: March 20, 2023
    Publication date: July 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
  • Patent number: 11682589
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Patent number: 11610982
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
  • Publication number: 20220085187
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.
    Type: Application
    Filed: January 4, 2021
    Publication date: March 17, 2022
    Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
  • Publication number: 20210043521
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Application
    Filed: October 12, 2020
    Publication date: February 11, 2021
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Patent number: 10804161
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Patent number: 10515807
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Fen Chien, Chih-Hsiang Fan, Hsiao-Kuan Wei, Pohan Kung, Hsien-Ming Lee
  • Publication number: 20190385855
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Fen CHIEN, Chih-Hsiang FAN, Hsiao-Kuan WEI, Pohan KUNG, Hsien-Ming LEE
  • Publication number: 20180174922
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Application
    Filed: November 3, 2017
    Publication date: June 21, 2018
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Patent number: 9898055
    Abstract: A data storage device securing mechanism includes a rack and a securing module. The rack includes a shell and two side plates connected to the ends of the shell. The securing module includes a slidable bracket on the rack and a magnetic latching member. The bracket includes two magnets of opposing poles against two magnetic blocks, and the latching member is rotatably installed on the side plate. When the bracket is slid in the rack, the two magnetic blocks are displaced adjacent to the latching member, to attract or to repel the latching member. The latching member is thereby rotated to approach or to move away from the side plate.
    Type: Grant
    Filed: December 18, 2016
    Date of Patent: February 20, 2018
    Assignees: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Chih-Hsiang Fan
  • Patent number: 9614307
    Abstract: A connector in an electronic device includes a case, a supporting element, and an elastic element. The case defines a through hole and a plurality of latching portions protruding from an inner surface of the case surrounding the through hole. The latching portions include an engaging surface and a guiding surface adjacent to the engaging surface. The supporting element is partially received in the through hole. The supporting element includes terminal recesses and resisting pieces engaging with the engaging surface. The elastic element is partially received in the supporting element and supplied a resilient force. When the supporting element is moved away from the case, the resisting piece is separated from the engaging surface to make contact with the guiding surface under the resilient force. If reassembly of the connector contacts is not in the predetermined order the electronic device will be locked down.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: April 4, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chih-Hsiang Fan, Ying-Jui Huang
  • Patent number: 9383785
    Abstract: A fixing element for hard disk drive includes a frame and a hard disk. The frame includes a bottom plate, a front plate, a rear plate and a side plate. The front plate has a flange extending horizontally and backwardly from the front plate. A first elastic element is formed on a bottom of the flange. A second elastic element is located at the bottom plate in a position directly under the first elastic element. The supporting element defines an engaging groove at rear ends thereof. The engaging groove engages with a position element secured to the frame, the first elastic element is abutting an upper surface of the supporting element, and the second elastic element is abutting a bottom surface of the supporting element.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: July 5, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Chih-Hsiang Fan
  • Publication number: 20160066444
    Abstract: A connector in an electronic device includes a case, a supporting element, and an elastic element. The case defines a through hole and a plurality of latching portions protruding from an inner surface of the case surrounding the through hole. The latching portions include an engaging surface and a guiding surface adjacent to the engaging surface. The supporting element is partially received in the through hole. The supporting element includes terminal recesses and resisting pieces engaging with the engaging surface. The elastic element is partially received in the supporting element and supplied a resilient force. When the supporting element is moved away from the case, the resisting piece is separated from the engaging surface to make contact with the guiding surface under the resilient force. If reassembly of the connector contacts is not in the predetermined order the electronic device will be locked down.
    Type: Application
    Filed: August 19, 2015
    Publication date: March 3, 2016
    Inventors: CHIH-HSIANG FAN, YING-JUI HUANG
  • Patent number: 9152189
    Abstract: A locking mechanism is used to lock a removable electronic device on a housing structure including a pair of resisting portions. The locking mechanism includes a pair of bar members, a pair of elastic elements and an operating member. Each of the pair of bar members includes a blocking portion to engage with the corresponding resisting portion and a matching portion. The pair of elastic elements is elastically connected between the electronic device and the corresponding bar members. The operating member located between the pair of bar members and defines a first groove and a second groove respectively engaging with the matching portions.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: October 6, 2015
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Chih-Hsiang Fan
  • Publication number: 20140312197
    Abstract: A fixing element for hard disk drive includes a frame and a hard disk. The frame includes a bottom plate, a front plate, a rear plate and a side plate. The front plate has a flange extending horizontally and backwardly from the front plate. A first elastic element is formed on a bottom of the flange. A second elastic element is located at the bottom plate in a position directly under the first elastic element. The supporting element defines an engaging groove at rear ends thereof. The engaging groove engages with a position element secured to the frame, the first elastic element is abutting an upper surface of the supporting element, and the second elastic element is abutting a bottom surface of the supporting element.
    Type: Application
    Filed: May 16, 2013
    Publication date: October 23, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHIH-HSIANG FAN
  • Publication number: 20120213577
    Abstract: A locking mechanism is used to lock a removable electronic device on a housing structure including a pair of resisting portions. The locking mechanism includes a pair of bar members, a pair of elastic elements and an operating member. Each of the pair of bar members includes a blocking portion to engage with the corresponding resisting portion and a matching portion. The pair of elastic elements is elastically connected between the electronic device and the corresponding bar members. The operating member located between the pair of bar members and defines a first groove and a second groove respectively engaging with the matching portions.
    Type: Application
    Filed: June 13, 2011
    Publication date: August 23, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHIH-HSIANG FAN