Patents by Inventor Chih-Hsiang Huang

Chih-Hsiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12356660
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: July 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su, Chih-Hsiang Huang
  • Publication number: 20250218779
    Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a stack of channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shape structure, forming a dummy gate stack over a channel region of the fin-shape structure, recessing a source/drain region to form a source/drain trench, forming an epitaxial feature in the source/drain trench, after the forming of the epitaxial feature removing the dummy gate stack, releasing the channel layers in the channel region as channel members, forming a gate structure wrapping around each of the channel members, and after the forming of the gate structure performing an ion implantation to increase a dopant concentration of a dopant in the epitaxial feature.
    Type: Application
    Filed: May 7, 2024
    Publication date: July 3, 2025
    Inventors: Shih-Hao Lin, Jui-Lin Chen, Chih-Hsiang Huang
  • Publication number: 20250204014
    Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a dielectric layer over a portion of a substrate, forming an aluminum-containing work function layer over the dielectric layer, where a concentration of aluminum in a first portion of the aluminum-containing work function layer is different than the concentration of aluminum in a second portion of the aluminum-containing work function layer, and forming a metal layer over the aluminum-containing work function layer.
    Type: Application
    Filed: April 6, 2024
    Publication date: June 19, 2025
    Inventors: Shih-Hao Lin, Chih-Hsiang Huang
  • Patent number: 12213297
    Abstract: A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (Vt) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Hsiang Huang, Shang-Rong Li, Chih-Chuan Yang, Jui-Lin Chen, Ming-Shuan Li
  • Publication number: 20240413018
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: December 12, 2024
    Inventors: Shih-Hao Lin, Tzu-Hsiang Hsu, Chong-De Lien, Szu-Chi Yang, Hsin-Wen Su, Chih-Hsiang Huang
  • Publication number: 20240397694
    Abstract: A semiconductor structure includes a substrate, first channel layers vertically stacked over the substrate in a first region, and second channel layers vertically stacked over the substrate in a second region. The first and second regions have opposite conductivity types. The semiconductor structure also includes a threshold voltage (Vt) modulation layer wrapping around each of the second channel layers in the second region. The first region is free of the Vt modulation layer. The semiconductor structure also includes a gate dielectric layer wrapping around each of the first channel layers and the second channel layers over the Vt modulation layer, and a work function metal layer disposed on the gate dielectric layer and wrapping around each of the first channel layers and the second channel layers.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Shih-Hao Lin, Chih-Hsiang Huang, Shang-Rong Li, Chih-Chuan Yang, Jui-Lin Chen, Ming-Shuan Li
  • Patent number: 12112989
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hao Lin, Tzu-Hsiang Hsu, Chong-De Lien, Szu-Chi Yang, Hsin-Wen Su, Chih-Hsiang Huang
  • Publication number: 20240250174
    Abstract: A device includes a gate structure extending over a semiconductor channel region, and source/drain epitaxial structures at opposite sides of the gate structure. Each of the source/drain epitaxial structures includes a bar-shaped epitaxial region and a cladding epitaxial layer cladding on the bar-shaped epitaxial region, the cladding epitaxial layer having a dopant concentration higher than a dopant concentration of the bar-shaped epitaxial region.
    Type: Application
    Filed: March 5, 2024
    Publication date: July 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Chi YANG, Chih-Hsiang HUANG
  • Patent number: 11949015
    Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate structure is formed extending across the semiconductor fin. Recesses are etched in the semiconductor fin. Source/drain epitaxial structures are formed in the recesses in the semiconductor fin. Formation of each of the source/drain epitaxial structures comprises performing a first epitaxy growth process to form a bar-shaped epitaxial structure in one of the recesses, and performing a second epitaxy growth process to form a cladding epitaxial layer cladding on the bar-shaped epitaxial structure. The bar-shaped epitaxial structure has a lower phosphorous concentration than the cladding epitaxial layer.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Chi Yang, Chih-Hsiang Huang
  • Patent number: 11949016
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su, Chih-Hsiang Huang
  • Publication number: 20230378298
    Abstract: A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members, the source/drain feature comprising an undoped bottom layer and a doped upper layer, where a part of the undoped bottom layer of the source/drain feature is disposed directly under the gate structure.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Shang-Rong Li, Shih-Hao Lin, Chih-Hsiang Huang
  • Publication number: 20230378365
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 23, 2023
    Inventors: Shih-Hao LIN, Chih-Chuan YANG, Chih-Hsuan CHEN, Bwo-Ning CHEN, Cha-Hon CHOU, Hsin-Wen SU, Chih-Hsiang HUANG
  • Patent number: 11581226
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hao Lin, Tzu-Hsiang Hsu, Chong-De Lien, Szu-Chi Yang, Hsin-Wen Su, Chih-Hsiang Huang
  • Publication number: 20220416046
    Abstract: A method of manufacturing a semiconductor device includes forming a fin, the fin having an epitaxial portion and a base portion protruding from a substrate. Sidewalls of the base portion are tapered with respect to sidewalls of the epitaxial portion. The method also includes depositing a polymeric material on the sidewalls of the epitaxial portion, performing an etching process to modify a profile of the sidewalls of the base portion, such that the sidewalls of the base portion are laterally recessed with a narrowest width of the base portion located under a top surface of the base portion, removing the polymeric material from the sidewalls of the epitaxial portion, depositing an isolation feature on the sidewalls of the base portion, and forming a gate structure engaging the epitaxial portion.
    Type: Application
    Filed: April 15, 2022
    Publication date: December 29, 2022
    Inventors: Shang-Rong Li, Shih-Hao Lin, Wen-Chun Keng, Chih-Chuan Yang, Chih-Hsiang Huang, Ping-Wei Wang
  • Publication number: 20220384655
    Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate structure is formed extending across the semiconductor fin. Recesses are etched in the semiconductor fin. Source/drain epitaxial structures are formed in the recesses in the semiconductor fin. Formation of each of the source/drain epitaxial structures comprises performing a first epitaxy growth process to form a bar-shaped epitaxial structure in one of the recesses, and performing a second epitaxy growth process to form a cladding epitaxial layer cladding on the bar-shaped epitaxial structure. The bar-shaped epitaxial structure has a lower phosphorous concentration than the cladding epitaxial layer.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Chi YANG, Chih-Hsiang HUANG
  • Publication number: 20220367726
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Inventors: Shih-Hao LIN, Chih-Chuan YANG, Chih-Hsuan CHEN, Bwo-Ning CHEN, Cha-Hon CHOU, Hsin-Wen SU, Chih-Hsiang HUANG
  • Publication number: 20220359308
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Shih-Hao Lin, Tzu-Hsiang Hsu, Chong-De Lien, Szu-Chi Yang, Hsin-Wen Su, Chih-Hsiang Huang
  • Publication number: 20220352180
    Abstract: A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (Vt) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.
    Type: Application
    Filed: September 1, 2021
    Publication date: November 3, 2022
    Inventors: Shih-Hao Lin, Chih-Hsiang Huang, Shang-Rong Li, Chih-Chuan Yang, Jui-Lin Chen, Ming-Shuan Li
  • Patent number: 11437516
    Abstract: A semiconductor structure includes a gate structure disposed over a substrate, and a plurality of source/drain features disposed on the substrate and interposed by the gate structure. Each of the source/drain features includes a first doped source/drain region extended away from the substrate, and a second doped source/drain region disposed on top and side surfaces of the first doped source/drain region, in which a phosphorus doping concentration of the first doped source/drain region is lower than a doping concentration of the second doped source/drain region.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Chi Yang, Chih-Hsiang Huang
  • Publication number: 20210098311
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.
    Type: Application
    Filed: July 24, 2020
    Publication date: April 1, 2021
    Inventors: Shih-Hao Lin, Tzu-Hsiang Hsu, Chong-De Lien, Szu-Chi Yang, Hsin-Wen Su, Chih-Hsiang Huang