Patents by Inventor Chih-Hsiang Su

Chih-Hsiang Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250124979
    Abstract: A control device, for controlling an operation of a memory device, wherein the memory device includes a plurality of memory blocks, each of the memory blocks includes a plurality of memory cells, and each of the memory cells stores a bit-data. The control device comprises the following elements. A processor, for classifying the memory cells into a plurality of groups according to an erase count of each of the memory cells, the groups respectively correspond to a plurality of recovery times. A memory interface control circuit, coupled to the processor and the memory device, and the processor controls the memory device to perform a bit recovery operation through the memory interface control circuit. The processor selects one of the groups according to the recovery times, and performs the bit recovery operation on the bit-data of each of the memory cells in the selected group.
    Type: Application
    Filed: October 11, 2023
    Publication date: April 17, 2025
    Inventors: Wei-Cheng SU, Chih-Hsiang YANG, Hsiang-Lan LUNG
  • Patent number: 12277332
    Abstract: The application provides a method and a memory device for performing wear leveling in a memory device. The method includes: receiving data to be written transmitted by a host in the memory device; predicting the data to be written as a first type of data or a second type of data; referencing an erase count table in an erase count table buffer of the memory device; and when the data to be written is predicted as the first type of data, writing the data to be written into the block with a highest erase count among these blocks, and when the data to be written is predicted as the second type of data, writing the data to be written into the block with a lowest erase count among these blocks.
    Type: Grant
    Filed: August 18, 2023
    Date of Patent: April 15, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Cheng Su, Chih-Hsiang Yang, Hsiang-Lan Lung
  • Publication number: 20250076950
    Abstract: A power management system includes at least one device, at least one memory management unit (MMU), a processor, and at least one device controller, wherein the at least one MMU corresponds to the at least one device, respectively. The processor is arranged to execute at least one access control power manager, an operating system (OS), and a hypervisor, wherein the OS is arranged to generate a trigger signal, and the hypervisor is arranged to generate a first hint according to the trigger signal. The at least one device controller is arranged to control the at least one access control power manager according to the first hint, to manage at least one power of the at least one MMU.
    Type: Application
    Filed: September 4, 2023
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chih-Hsiang Hsiao, Chih-Pin Su
  • Publication number: 20250060892
    Abstract: The application provides a method and a memory device for performing wear leveling in a memory device. The method includes: receiving data to be written transmitted by a host in the memory device; predicting the data to be written as a first type of data or a second type of data; referencing an erase count table in an erase count table buffer of the memory device; and when the data to be written is predicted as the first type of data, writing the data to be written into the block with a highest erase count among these blocks, and when the data to be written is predicted as the second type of data, writing the data to be written into the block with a lowest erase count among these blocks.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Inventors: Wei-Cheng SU, Chih-Hsiang YANG, Hsiang-Lan LUNG
  • Patent number: 8808492
    Abstract: A method of joining superconductor materials is described. A microwave chamber including a first heat absorption plate and a second heat absorption plate corresponding to the first absorption plate is provided. A first superconductor material and a second superconductor material are disposed between the first heat absorption plate and the second heat absorption plate in the microwave chamber. The first superconductor material and the second superconductor material have an overlapping region therebetween, and a pressure is applied to the first heat absorption plate and the second heat absorption plate. Microwave power is supplied to the microwave chamber. The first heat absorption plate and the second heat absorption plate transform the microwave power into thermal energy so as to join the first superconductor material and the second superconductor material at the overlapping region.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: August 19, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Kun-Ping Huang, Chih-Chen Chang, Yu-Tse Hsieh, Chih-Wei Luo, Chih-Hsiang Su, Wen-Yen Tzeng
  • Publication number: 20130157868
    Abstract: A method of joining superconductor materials is described. A microwave chamber including a first heat absorption plate and a second heat absorption plate corresponding to the first absorption plate is provided. A first superconductor material and a second superconductor material are disposed between the first heat absorption plate and the second heat absorption plate in the microwave chamber. The first superconductor material and the second superconductor material have an overlapping region therebetween, and a pressure is applied to the first heat absorption plate and the second heat absorption plate. Microwave power is supplied to the microwave chamber. The first heat absorption plate and the second heat absorption plate transform the microwave power into thermal energy so as to join the first superconductor material and the second superconductor material at the overlapping region.
    Type: Application
    Filed: June 6, 2012
    Publication date: June 20, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kun-Ping Huang, Chih-Chen Chang, Yu-Tse Hsieh, Chih-Wei Luo, Chih-Hsiang Su, Wen-Yen Tzeng