Patents by Inventor Chih-Hsiang Su
Chih-Hsiang Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240413018Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.Type: ApplicationFiled: July 29, 2024Publication date: December 12, 2024Inventors: Shih-Hao Lin, Tzu-Hsiang Hsu, Chong-De Lien, Szu-Chi Yang, Hsin-Wen Su, Chih-Hsiang Huang
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Publication number: 20240413087Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.Type: ApplicationFiled: July 31, 2024Publication date: December 12, 2024Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
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Patent number: 12165975Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.Type: GrantFiled: July 13, 2023Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
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Patent number: 12153815Abstract: The application discloses a semiconductor memory device and a data storage method. When determining that an input data conforms to a target format, an input data vector is generated based on the input data. When determining that the input data is similar to a stored data in a target block of the memory array, the input data is written to a blank target memory page of the target block of the memory array.Type: GrantFiled: November 16, 2023Date of Patent: November 26, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wei-Cheng Su, Chih-Hsiang Yang, Hsiang-Lan Lung
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Publication number: 20240379430Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Shu-Cheng Chin, Chih-Yi Chang, Wei Hsiang Chan, Chih-Chien Chi, Chi-Feng Lin, Hung-Wen Su
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Patent number: 12112989Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.Type: GrantFiled: July 26, 2022Date of Patent: October 8, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hao Lin, Tzu-Hsiang Hsu, Chong-De Lien, Szu-Chi Yang, Hsin-Wen Su, Chih-Hsiang Huang
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Publication number: 20240314334Abstract: Aspects of the present disclosure provide a video playback system. For example, the video playback system can include a video controller configured to receive one or more video frames and partition each of the video frames into a plurality of video tiles, a video decoder configured to decode one of the video tiles partitioned from each of the video frames, an artificial intelligence (AI) accelerator configured to execute an executable AI model on the decoded video tile, a display configured to display the processed video tile, and a pipeline manager installed in the video controller. The pipeline manager can be configured to control the video decoder to decode the video tile, control the AI accelerator to execute the executable AI model on the decoded video tile, and control the display to display the processed video tile.Type: ApplicationFiled: January 25, 2024Publication date: September 19, 2024Applicant: MEDIATEK INC.Inventors: Hsu CHIA-FENG, Chih-Hsiang HSIAO, Shih-Yong SU
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Patent number: 12061923Abstract: A system includes a memory addressable by addresses within a physical address (PA) space, and one or more processors that perform operations of virtual machines (VMs). The VMs are allocated with extended PA regions outside the PA space. The system further includes a memory interface controller coupled to the memory and the one or more processors. The memory interface controller receives a request for accessing an address in the extended PA regions from a requesting VM, and uses a remap circuit to map the address in the extended PA regions to a remapped address in the PA space. A memory protection unit (MPU) in the memory interface controller grants or denies the request based on stored information indicating whether the remapped address is accessible to the requesting VM.Type: GrantFiled: November 11, 2021Date of Patent: August 13, 2024Assignee: MediaTek Inc.Inventors: Chih-Hsiang Hsiao, Chih-Pin Su
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Patent number: 8808492Abstract: A method of joining superconductor materials is described. A microwave chamber including a first heat absorption plate and a second heat absorption plate corresponding to the first absorption plate is provided. A first superconductor material and a second superconductor material are disposed between the first heat absorption plate and the second heat absorption plate in the microwave chamber. The first superconductor material and the second superconductor material have an overlapping region therebetween, and a pressure is applied to the first heat absorption plate and the second heat absorption plate. Microwave power is supplied to the microwave chamber. The first heat absorption plate and the second heat absorption plate transform the microwave power into thermal energy so as to join the first superconductor material and the second superconductor material at the overlapping region.Type: GrantFiled: June 6, 2012Date of Patent: August 19, 2014Assignee: Industrial Technology Research InstituteInventors: Kun-Ping Huang, Chih-Chen Chang, Yu-Tse Hsieh, Chih-Wei Luo, Chih-Hsiang Su, Wen-Yen Tzeng
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Publication number: 20130157868Abstract: A method of joining superconductor materials is described. A microwave chamber including a first heat absorption plate and a second heat absorption plate corresponding to the first absorption plate is provided. A first superconductor material and a second superconductor material are disposed between the first heat absorption plate and the second heat absorption plate in the microwave chamber. The first superconductor material and the second superconductor material have an overlapping region therebetween, and a pressure is applied to the first heat absorption plate and the second heat absorption plate. Microwave power is supplied to the microwave chamber. The first heat absorption plate and the second heat absorption plate transform the microwave power into thermal energy so as to join the first superconductor material and the second superconductor material at the overlapping region.Type: ApplicationFiled: June 6, 2012Publication date: June 20, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kun-Ping Huang, Chih-Chen Chang, Yu-Tse Hsieh, Chih-Wei Luo, Chih-Hsiang Su, Wen-Yen Tzeng