Patents by Inventor Chih-Hsiao Chen

Chih-Hsiao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10727113
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • Publication number: 20200111909
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
  • Publication number: 20200111702
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • Patent number: 10510882
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 10504775
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • Publication number: 20190371655
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • Patent number: 10359692
    Abstract: A laser illumination system and a method for eliminating laser speckles thereof are revealed. The laser illumination system includes laser module emitting a laser beam, a scanning unit for scanning the laser beam to form scanning beams, and a diffractive optical element which the scanning beams are passed through to form illuminating beams that are projected to an area to be illuminated or an object. Thus an image detecting unit can capture an image of the area or the object. The scanning beams are converted into the illuminating beams by the diffractive optical element that causes changes in spatial phase redistribution or light energy distribution thereof. One point in the area or on the object shows energy of partial light of at least two of the laser beams. Thus a laser speckle of the image can be eliminated by the superposition of the energy of the partial light.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 23, 2019
    Assignee: NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventor: Chih-Hsiao Chen
  • Publication number: 20190064539
    Abstract: A laser illumination system and a method for eliminating laser speckles thereof are revealed. The laser illumination system includes laser module emitting a laser beam, a scanning unit for scanning the laser beam to form scanning beams, and a diffractive optical element which the scanning beams are passed through to form illuminating beams that are projected to an area to be illuminated or an object. Thus an image detecting unit can capture an image of the area or the object. The scanning beams are converted into the illuminating beams by the diffractive optical element that causes changes in spatial phase redistribution or light energy distribution thereof. One point in the area or on the object shows energy of partial light of at least two of the laser beams. Thus a laser speckle of the image can be eliminated by the superposition of the energy of the partial light.
    Type: Application
    Filed: January 8, 2018
    Publication date: February 28, 2019
    Inventor: Chih-Hsiao CHEN
  • Patent number: 9691867
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang, Yao-Yu Li
  • Publication number: 20160359010
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO.,LTD.
    Inventors: Chen-Liang LIAO, Chih-Hsiao CHEN, Yi-lii HUANG, Yao-Yu LI
  • Patent number: 9425274
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang, Yao-Yu Li
  • Publication number: 20160203984
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang LIAO, Chih-Hsiao CHEN, Yi-Lii HUANG, Yao-Yu LI
  • Patent number: 9349817
    Abstract: Embodiments of the disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: May 24, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang, Yao-Yu Li
  • Patent number: 9324864
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes an isolation structure positioned in the semiconductor substrate and adjacent to a first active region of the semiconductor substrate. The semiconductor device structure includes a gate stack disposed over the first active region. The semiconductor device structure includes a first contact structure disposed over the first active region and positioned between the isolation structure and the gate stack. The semiconductor device structure includes a dummy gate stack disposed over the isolation structure and adjacent to the gate stack. The dummy gate stack is not positioned over a portion of the isolation structure next to the first contact structure.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yao Liang, Chen-Liang Liao, Ming Lei, Chih-Hsiao Chen, Yi-Lii Huang
  • Publication number: 20160093736
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes an isolation structure positioned in the semiconductor substrate and adjacent to a first active region of the semiconductor substrate. The semiconductor device structure includes a gate stack disposed over the first active region. The semiconductor device structure includes a first contact structure disposed over the first active region and positioned between the isolation structure and the gate stack. The semiconductor device structure includes a dummy gate stack disposed over the isolation structure and adjacent to the gate stack. The dummy gate stack is not positioned over a portion of the isolation structure next to the first contact structure.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yao LIANG, Chen-Liang LIAO, Ming LEI, Chih-Hsiao CHEN, Yi-Lii HUANG
  • Publication number: 20150221737
    Abstract: Embodiments of the disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chen-Liang LIAO, Chih-Hsiao CHEN, Yi-Lii HUANG, Yao-Yu LI
  • Patent number: 8587451
    Abstract: A laser projection system including a projection screen and a laser projector is revealed. The projection screen includes at least one light emitting layer having at least one luminescent material that is excited by excitation light with a specific wavelength range to generate excited light with another wavelength range. The laser projector consists of a laser light source module, a laser signal modulation module, a rotation plane mirror module, a rotation plane mirror control module, and a signal conversion module. The laser projector produces excitation laser according to an image signal of a static image or dynamic image and projects the laser to the projection screen correspondingly for an image displayed. Thus a projected image with high recognition is displayed on the projection screen in a transparent manner in natural sunlight. Therefore efficiency and application of the laser projection are improved.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: November 19, 2013
    Assignee: ALVIS Technologies Inc.
    Inventor: Chih-Hsiao Chen
  • Publication number: 20110316721
    Abstract: A laser projection system including a projection screen and a laser projector is revealed. The projection screen includes at least one light emitting layer having at least one luminescent material that is excited by excitation light with a specific wavelength range to generate excited light with another wavelength range. The laser projector consists of a laser light source module, a laser signal modulation module, a rotation plane mirror module, a rotation plane mirror control module, and a signal conversion module. The laser projector produces excitation laser according to an image signal of a static image or dynamic image and projects the laser to the projection screen correspondingly for an image displayed. Thus a projected image with high recognition is displayed on the projection screen in a transparent manner in natural sunlight. Therefore efficiency and application of the laser projection are improved.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 29, 2011
    Inventor: Chih-Hsiao CHEN
  • Publication number: 20100231868
    Abstract: A display device is revealed. The display device includes a laser source for emitting a laser beam, a pre-optics for processing the laser beam, a light scan member such as a MEMS mirror for converting the processed laser beam into a scanning light beam, and/or a corresponding post-optics. A switch-control beam splitter is disposed on the light path of the laser beam, after the light scan member so as to divide the scanning light beam into a reflected light beam and a transmitted light beam. They are two different light paths and generate a virtual image as well as a real image respectively.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 16, 2010
    Inventors: Guo-Zen CHEN, Ming-Hua Wen, Chih-Hsiao Chen
  • Patent number: 7660532
    Abstract: A calibration method of an optical transceiver module includes the steps of receiving an input voltage, detecting an optical signal for generating an input power based on the optical signal, generating a compensating power based on the input voltage, and generating a calibrating power based on the compensating power and the input power.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: February 9, 2010
    Assignee: Delta Electronics Inc.
    Inventors: Chien-Shu Chiu, Yung-Yuan Cheng, Chiung-Hung Wang, Chih-Hsiao Chen