Patents by Inventor Chih-Hsien Shen

Chih-Hsien Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220005754
    Abstract: A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 6, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ren-Shin CHENG, Shih-Hsien WU, Yu-Wei HUANG, Chih Ming SHEN, Yi-Chieh TSAI
  • Patent number: 10483845
    Abstract: The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: November 19, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yu-Li Hsueh, Chih-Hsien Shen, Chao-Ching Hung, Po-Chun Huang
  • Publication number: 20190199207
    Abstract: The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.
    Type: Application
    Filed: September 20, 2018
    Publication date: June 27, 2019
    Inventors: Yu-Li Hsueh, Chih-Hsien Shen, Chao-Ching Hung, Po-Chun Huang
  • Patent number: 9853648
    Abstract: A compensation apparatus including a primary circuit and a compensation circuit is provided. The primary circuit provides a first voltage, a second voltage, and a first current flowing through a first inductor. The primary circuit includes the first inductor and a function circuit generating an input signal. The first inductor is coupled between a first terminal with the first voltage and a second terminal with the second voltage. The compensation circuit includes a second inductor and a current source circuit. The second inductor is coupled between a third terminal with a third voltage and a fourth terminal with a fourth voltage. The current source circuit outputs a second current flowing through the second inductor. The current source circuit adjusts a frequency of the input signal. The primary circuit and the compensation circuit are coupled via the first inductor and the second inductor.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: December 26, 2017
    Assignee: MEDIATEK INC.
    Inventors: Richard Y. Su, Yu-Li Hsueh, Chih-Hsien Shen, Chao-Ching Hung, Yi-Chien Tsai
  • Publication number: 20160118903
    Abstract: A compensation apparatus including a primary circuit and a compensation circuit is provided. The primary circuit provides a first voltage, a second voltage, and a first current flowing through a first inductor. The primary circuit includes the first inductor and a function circuit generating an input signal. The first inductor is coupled between a first terminal with the first voltage and a second terminal with the second voltage. The compensation circuit includes a second inductor and a current source circuit. The second inductor is coupled between a third terminal with a third voltage and a fourth terminal with a fourth voltage. The current source circuit outputs a second current flowing through the second inductor. The current source circuit adjusts a frequency of the input signal. The primary circuit and the compensation circuit are coupled via the first inductor and the second inductor.
    Type: Application
    Filed: June 12, 2015
    Publication date: April 28, 2016
    Inventors: Richard Y. Su, Yu-Li Hsueh, Chih-Hsien Shen, Chao-Ching Hung, Yi-Chien Tsai
  • Patent number: 9100083
    Abstract: A radio-frequency (RF) front-end supporting at least a first and second wireless communication bands includes a mixer arranged for mixing a received signal with a first local oscillation signal when the shared receiver front-end performs the reception operation according to the first wireless communication band, and for mixing the received signal with a second local oscillation signal when the shared receiver front-end performs the reception operation according to the second wireless communication band, wherein the first and second local oscillation signals are different in frequency.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: August 4, 2015
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hsin Wu, Chih-Hsien Shen, Jui-Lin Hsu, Chih-Hung Lee, Yi-An Li
  • Patent number: 8878582
    Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Mediatek Inc.
    Inventors: Yu-Li Hsueh, Chih-Hsien Shen, Jing-Hong Conan Zhan
  • Patent number: 8791732
    Abstract: A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: July 29, 2014
    Assignee: MediaTek Inc.
    Inventors: Jui-Lin Hsu, Chih-Hsien Shen, Chunwei Chang, Jing-Hong Conan Zhan
  • Patent number: 8761025
    Abstract: A method used for testing the communication performance of a plurality of wireless signal access devices, and the steps of the testing method of each wireless signal access device include: (a). booting up the wireless signal access device; (b). activating said the wireless signal access device to transmit or receive testing packets to test the communication performance of the wireless signal access device. The feature of the present invention lies in completing a step a of the next wireless signal access device before completing a step b of a first wireless signal access device, and starting the step b of the next wireless signal access device in an appropriate timing after completing the step b of the first wireless signal access device, thereby reaching the goal of reducing the test time.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: June 24, 2014
    Assignee: Accton Technology Corporation
    Inventors: Chien-Lung Lee, Yi-Ming Wang, Chih-Hsien Shen
  • Patent number: 8674772
    Abstract: An oscillating signal generator utilized in a phase-locked loop (PLL) includes: an oscillating circuit arranged to generate an oscillating signal according to at least a first control signal; and a control circuit, arranged to adjust the first control signal according to a temperature; and the first control signal is tuned between a first boundary and a second boundary, and when the temperature is closer to a first temperature boundary than a second temperature boundary, and the control circuit is arranged to make the first control signal to be closer to the first boundary than the second boundary such that the oscillating circuit outputs the oscillating signal of a predetermined frequency in a locked mode of the PLL.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 18, 2014
    Assignee: Mediatek Inc.
    Inventor: Chih-Hsien Shen
  • Publication number: 20130309979
    Abstract: A radio-frequency (RF) front-end supporting at least a first and second wireless communication bands includes a mixer arranged for mixing a received signal with a first local oscillation signal when the shared receiver front-end performs the reception operation according to the first wireless communication band, and for mixing the received signal with a second local oscillation signal when the shared receiver front-end performs the reception operation according to the second wireless communication band, wherein the first and second local oscillation signals are different in frequency.
    Type: Application
    Filed: March 12, 2013
    Publication date: November 21, 2013
    Applicant: MEDIATEK INC.
    Inventors: Chia-Hsin Wu, Chih-Hsien Shen, Jui-Lin Hsu, Chih-Hung Lee, Yi-An Li
  • Publication number: 20130141149
    Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.
    Type: Application
    Filed: September 12, 2012
    Publication date: June 6, 2013
    Applicant: MEDIATEK INC.
    Inventors: Yu-Li HSUEH, Chih-Hsien SHEN, Jing-Hong Conan ZHAN
  • Publication number: 20120286391
    Abstract: A semiconductor circuit is provided. The semiconductor circuit includes a metal layer, a conductive layer disposed under the metal layer and a semiconductor device disposed under the conductive layer. The metal layer forms an inductor device. The semiconductor device is coupled to the inductor device.
    Type: Application
    Filed: November 8, 2011
    Publication date: November 15, 2012
    Applicant: MediaTek Inc.
    Inventors: Chih-Hsien Shen, Jui-Lin Hsu, Chunwei Chang, Jing-Hong Conan Zhan
  • Publication number: 20120286834
    Abstract: A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal.
    Type: Application
    Filed: November 8, 2011
    Publication date: November 15, 2012
    Applicant: MEDIATEK INC.
    Inventors: Jui-Lin Hsu, Chih-Hsien Shen, Chunwei Chang, Jing-Hong Conan Zhan
  • Publication number: 20120249249
    Abstract: An oscillating signal generator utilized in a phase-locked loop (PLL) includes: an oscillating circuit arranged to generate an oscillating signal according to at least a first control signal; and a control circuit, arranged to adjust the first control signal according to a temperature; and the first control signal is tuned between a first boundary and a second boundary, and when the temperature is closer to a first temperature boundary than a second temperature boundary, and the control circuit is arranged to make the first control signal to be closer to the first boundary than the second boundary such that the oscillating circuit outputs the oscillating signal of a predetermined frequency in a locked mode of the PLL.
    Type: Application
    Filed: March 26, 2012
    Publication date: October 4, 2012
    Inventor: Chih-Hsien Shen
  • Publication number: 20120243419
    Abstract: A method used for testing the communication performance of a plurality of wireless signal access devices, and the steps of the testing method of each wireless signal access device include: (a). booting up the wireless signal access device; (b). activating said the wireless signal access device to transmit or receive testing packets to test the communication performance of the wireless signal access device. The feature of the present invention lies in completing a step a of the next wireless signal access device before completing a step b of a first wireless signal access device, and starting the step b of the next wireless signal access device in an appropriate timing after completing the step b of the first wireless signal access device, thereby reaching the goal of reducing the test time.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 27, 2012
    Inventors: CHIEN-LUNG LEE, YI-MING WANG, CHIH-HSIEN SHEN
  • Patent number: 7737797
    Abstract: A controllable oscillating system for generating a differential oscillating signal is disclosed. The controllable oscillating system includes an oscillating circuit and a current adjusting device. The oscillating circuit includes a controllable resonator, a cross-coupling driving device, and a current source. The cross-coupling driving device is coupled to the controllable resonator and utilized for driving the controllable resonator to generate the differential oscillating signal. The current source is coupled to the cross-coupling driving device and utilized for providing a first current. The current adjusting device is coupled to the cross-coupling driving device and utilized for adjusting currents passing through the cross-coupling driving device.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: June 15, 2010
    Assignee: Mediatek Inc.
    Inventor: Chih-Hsien Shen
  • Publication number: 20090115540
    Abstract: A controllable oscillating system for generating a differential oscillating signal is disclosed. The controllable oscillating system includes an oscillating circuit and a current adjusting device. The oscillating circuit includes a controllable resonator, a cross-coupling driving device, and a current source. The cross-coupling driving device is coupled to the controllable resonator and utilized for driving the controllable resonator to generate the differential oscillating signal. The current source is coupled to the cross-coupling driving device and utilized for providing a first current. The current adjusting device is coupled to the cross-coupling driving device and utilized for adjusting currents passing through the cross-coupling driving device.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 7, 2009
    Inventor: Chih-Hsien Shen
  • Patent number: 7271649
    Abstract: A DC offset calibration device for calibrating a DC offset of an output signal of a gain stage, the DC offset calibration device includes: a digital-to-analog converter (DAC) electrically connected to the gain stage for generating an offset current according to the DC offset of the output signal of the gain stage; and a current-to-current converter electrically connected to the DAC and the gain stage for reducing the signal scale of the offset current to generate a compensation signal so as to reduce the DC offset at the output of the gain stage.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: September 18, 2007
    Assignee: Mediatek Inc.
    Inventors: Chinq-Shiun Chiu, Chih-Hsien Shen, Shou-Tsung Wang, Chi-Kun Chiu
  • Publication number: 20060077003
    Abstract: A DC offset calibration device for calibrating a DC offset of an output signal of a gain stage, the DC offset calibration device includes: a digital-to-analog converter (DAC) electrically connected to the gain stage for generating an offset current according to the DC offset of the output signal of the gain stage; and a current-to-current converter electrically connected to the DAC and the gain stage for reducing the signal scale of the offset current to generate a compensation signal so as to reduce the DC offset at the output of the gain stage.
    Type: Application
    Filed: September 27, 2005
    Publication date: April 13, 2006
    Inventors: Chinq-Shiun Chiu, Chih-Hsien Shen, Shou-Tsung Wang, Chi-Kun Chiu