Abstract: A method and resulting integrated circuit device, and in particular a CMOS integrated circuit device, having a fabrication method and structure therefor for an improved lightly doped drain region. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectic over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 45.degree. or greater from a perpendicular to the gate electrodes in both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well region. Sidewall spacers are then formed on edges of the gate electrodes. The method then performs two separate N type implants into the P type well region, each at different angles and dosages to form the N type LDD source/drain region for an NMOS device.

Abstract: A method and structure therefor for the formation of lightly doped drain regions, typically used in the manufacture of a field effect devices. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 20 degrees and greater from a perpendicular to the gate electrodes into both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well, and a buried region in the N type well. Sidewall spacers are then formed on edges of the gate electrodes. An N type implant step is then performed on the P type well region to form the source/drain region of a NMOS device. The method then performs two separate P type implants into the N type well, each at different angles and dosages, to form the P type LDD source/drain region for a PMOS device.

Abstract: A method and structure therefor for the formation of lightly doped drain regions, typically used in the manufacture of a field effect devices. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 20 degrees and greater from a perpendicular to the gate electrodes into both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well, and a buried region in the N type well. Sidewall spacers are then formed on edges of the gate electrodes. An N type implant step is then performed on the P type well region to form the source/drain region of a NMOS device. The method then performs two separate P type implants into the N type well, each at different angles and dosages, to form the P type LDD source/drain region for a PMOS device.