Patents by Inventor Chih Hsin Wang

Chih Hsin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220146781
    Abstract: An optical component driving mechanism is provided, including a holder, a fixed portion, a driving assembly, and a first circuit assembly. The holder is used to connect the optical component. The holder is movable relative to the fixed portion. The driving assembly is used to drive the holder to move relative to the fixed portion. The first circuit assembly is fixedly disposed on the holder. The first circuit assembly is electrically connected to the driving assembly.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 12, 2022
    Inventors: Guan-Bo WANG, Shao-Chung CHANG, Chen-Hsin HUANG, Liang-Ting HO, Chih-Wen CHIANG, Kai-Po FAN
  • Patent number: 9895329
    Abstract: Disclosed herein are novel formyl peptide receptor 1 (FPR1) antagonists and their uses in manufacturing medicaments for the treatment and/or prophylaxis of diseases and/or disorders mediated by FPR1.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 20, 2018
    Inventors: Tsong-Long Hwang, Yung-Fong Tsai, Chun-Yu Chen, Liang-Mou Kuo, Yuan-Bin Cheng, Chih-Hsin Wang, Fang-Rong Chang, Yang-Chang Wu
  • Patent number: 8792274
    Abstract: A system is provided and includes an array of cells, a first module, and a third module. The first module reads a state of a cell in the array to detect first bits stored in the cell. The third module, subsequent to the first module reading the state, performs a first operation on a first bit of the first bits and performs the first operation on a first of multiple signal inputs. The signal inputs indicate second bits of data to be stored in the cell. The third module performs a second operation on a second bit of the first bits and performs the second operation on a second one of the signal inputs. The first module, based on results of the first and second operations, performs a first erase operation or a first program operation on the cell to match the state of the cell to the second bits.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: July 29, 2014
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Bo Wang, Chih-Hsin Wang
  • Patent number: 8270234
    Abstract: A level shifter including a level shifter module configured to i) receive an input signal, wherein the input signal varies between a first level and a second level, ii) receive a first voltage supply signal and a second voltage supply signal, and iii) generate a latch control signal based on the input signal and one of the first voltage supply signal and the second voltage supply signal. The level shifter further includes a latch module configured to i) receive the latch control signal, ii) receive the second voltage supply signal and a third voltage supply signal, and iii) generate an output signal based on the latch control signal and one of the second voltage supply signal and the third voltage supply signal.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: September 18, 2012
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Bo Wang, Chih-Hsin Wang
  • Patent number: 8264039
    Abstract: A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: September 11, 2012
    Assignee: Synopsys, Inc.
    Inventors: Bin Wang, William T. Colleran, Chih-Hsin Wang
  • Patent number: 8248848
    Abstract: A memory circuit includes a memory array with multi-level cells that are each capable of storing M bits of data, where M is an integer greater than one. A module reads a state of one of the multi-level cells. The module performs at least one of a first erase operation and a first program operation on the one of the multi-level cells for the M bits of data during a first time period.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: August 21, 2012
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Bo Wang, Chih-Hsin Wang
  • Patent number: 8120088
    Abstract: Memory cells and arrays have reduced bit line resistance. An element conductor is disposed on the top of the bit line to reduce the resistance of the bit line while maintaining a shallow bit line junction so that 200 Ohm/square or lower sheet resistances are achieved with the bit line junctions typically 20 nanometers or shallower while the doping levels in the junctions are below about 5×1019 atoms/cm3.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: February 21, 2012
    Assignee: Marvell International Ltd.
    Inventors: Min She, Chih-Hsin Wang
  • Patent number: 8113436
    Abstract: In one embodiment, a structure includes a semiconductor chip including a communication element for performing a wireless communication function where the communication element has a communication core occupying a region of the semiconductor chip, a plurality of chip pads with two of the chip pads electrically connected to the communication core; a chip carrier for carrying the semiconductor chip where the chip carrier includes a plurality of carrier pads with two of the carrier pads connected to the two chip pads; and an antenna connected to the carrier pads and electrically connected to the chip pads and to the communication core.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: February 14, 2012
    Assignee: RFMarq, Inc.
    Inventor: Chih-Hsin Wang
  • Patent number: 8116110
    Abstract: A memory device including nonvolatile memory cells arrayed in a first direction and in a second direction, a plurality of first lines extending in the first direction for coupling memory cells arrayed in the first direction, and a plurality of second lines extending in the second direction for coupling memory cells arrayed in the second direction. The memory device includes a plurality of decoders, including i) first decoders coupled to the first lines and ii) second decoders coupled to the second lines, for accessing any one or more of the memory cells in any order. The memory device includes a plurality of segments. Each segment includes different ones of the nonvolatile memory cells. A first one of the segments is juxtaposed to, in the second direction, a second one of the segments. The second one of the segments mirrors, in the second direction, the first one of the segments.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: February 14, 2012
    Assignee: Marvell International Ltd.
    Inventors: Pantas Sutardja, Chih-Hsin Wang, Qiang Tang
  • Patent number: 8072023
    Abstract: A memory device including a plurality of storage regions arranged with storage region intervals. A plurality of conductor lines are juxtaposed the storage region intervals. One or more isolations are provided, each isolation adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions. The storage regions are charge storage regions in memory cells and each memory cell further includes a first cell region, a second cell region and a cell channel juxtaposed the charge storage region and located between the first cell region and the second cell region. A first array region and a second array region are separated by a first one of the isolations; each array region includes one or more groups of the memory cells where each memory cell includes one of the storage regions.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: December 6, 2011
    Assignee: Marvell International Ltd.
    Inventor: Chih-Hsin Wang
  • Publication number: 20110158476
    Abstract: A robot and a method for recognizing human faces and gestures are provided, and the method is applicable to a robot. In the method, a plurality of face regions within an image sequence captured by the robot are processed by a first classifier, so as to locate a current position of a specific user from the face regions. Changes of the current position of the specific user are tracked to move the robot accordingly. While the current position of the specific user is tracked, a gesture feature of the specific user is extracted by analyzing the image sequence. An operating instruction corresponding to the gesture feature is recognized by processing the gesture feature through a second classifier, and the robot is controlled to execute a relevant action according to the operating instruction.
    Type: Application
    Filed: July 1, 2010
    Publication date: June 30, 2011
    Applicant: National Taiwan University of Science and Technology
    Inventors: Chin-Shyurng Fahn, Keng-Yu Chu, Chih-Hsin Wang
  • Patent number: 7948810
    Abstract: A level shifter includes a level shifter module that receives a first input signal having high and low states and at least one voltage supply signal, and that generates a latch control signal based on the high and low states of the first input signal. A latch module receives the latch control signal, a data input signal, and the at least one voltage supply signal. The latch module selectively stores data associated with the data input signal based on the latch control signal. The latch module selectively changes the at least one voltage supply signal from a first level to a second level and outputs the data according to the second level based on the latch control signal.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: May 24, 2011
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Bo Wang, Chih-Hsin Wang
  • Patent number: 7847374
    Abstract: A semiconductor device comprising a memory region including one or more transistor string arrays, a logic region including one or more logic transistors and an isolation region for isolating the logic transistors. The string array includes a plurality, T, of bipolar junction transistors. The string array includes a common collector region for the T bipolar junction transistors, a common base region for the T bipolar junction transistors, a plurality of emitters, one emitter for each of the T bipolar junction transistors, a number, B, of base contacts for the T bipolar junction transistors where the base contacts electrically couple the common base region and where the number of base contacts, B, is less than the number of transistors, T.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: December 7, 2010
    Inventor: Chih-Hsin Wang
  • Patent number: 7824981
    Abstract: A method comprises providing a first conductive region, arranging a second conductive region adjacent to and insulated from the first conductive region by a dielectric region, arranging a third region adjacent to and insulated from the second conductive region, and adjusting mechanical stress to at least one of the first conductive region and the second conductive region.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: November 2, 2010
    Inventor: Chih-Hsin Wang
  • Patent number: 7784688
    Abstract: A management system for tracking elements through steps and stages of a chain employing fixed tags permanently attached to elements that progress through the steps and stages. The elements are tracked by the fixed tags from an initial stage, through multiple work-in-process stages to a final stage of the chain. The fixed tags include radio-frequency (RF) communication units that have wireless communication with RF communicators in one or more of the stages of the supply chain. The wireless communications between the RF tags and the RF communicators operate with a tag communication protocol that defines the operations and sequences for storing information into and retrieval of information from tags. The hierarchy of data storage in RF tags, in RF communicators and otherwise in storage locations in the system is controlled to operate within the memory hierarchy.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: August 31, 2010
    Assignee: RFMarq, Inc.
    Inventor: Chih-Hsin Wang
  • Patent number: 7759719
    Abstract: A nonvolatile memory cell is provided. The cell has a charge filter, a tunneling gate, a ballistic gate, a charge storage layer, a source, and a drain with a channel defined between the source and drain. The charge filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage layer while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. Further embodiments of the present invention provide a cell having a charge filter, a supplier gate, a tunneling gate, a ballistic gate, a source, a drain, a channel, and a charge storage layer. The present invention further provides an energy band engineering method permitting the memory cell be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: July 20, 2010
    Inventor: Chih-Hsin Wang
  • Patent number: 7745286
    Abstract: A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the channel; arranging a charge storage region adjacent to the first insulator layer; arranging a second insulator layer adjacent to the charge storage region; arranging a first conductive region adjacent to the second insulator layer; arranging a filter adjacent to the first conductive region; and arranging a second conductive region adjacent to the filter. The second conductive region overlaps the first conductive region at an overlap surface. A line perpendicular to the overlap surface intersects at least a portion of the charge storage region.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: June 29, 2010
    Inventor: Chih-Hsin Wang
  • Patent number: 7746704
    Abstract: A system includes an input that receives a control signal and a program module that initializes a nonvolatile multilevel memory cell based on the control signal. The program module initializes the nonvolatile multilevel memory cell by programming the nonvolatile multilevel memory cell to one of S states of the nonvolatile multilevel memory cell, where S is an integer greater than 1. The one of the S states is different than a lowest one of the S states.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: June 29, 2010
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Bo Wang, Chih-Hsin Wang
  • Patent number: 7741177
    Abstract: A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the substrate; arranging a charge storage region adjacent to the first insulator layer; arranging a second insulator layer adjacent to the charge storage region; arranging a first conductive region adjacent to the second insulator layer; arranging a layer adjacent to the first conductive region; arranging a second conductive region adjacent to the layer; and increasing mechanical stress of at least one of the first and second conductive regions. The second conductive region overlaps the first conductive region at an overlap surface, and wherein a line perpendicular to the overlap surface intersects at least a portion of the charge storage region.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: June 22, 2010
    Inventor: Chih-Hsin Wang
  • Patent number: 7724596
    Abstract: A sensing amplifier for a memory cell comprises a selection stage that outputs one of a reference current and a memory cell current during a first period and the other of the reference current and the memory cell current during a second period. The first period and the second period are non-overlapping. An input stage generates a first current based on the one of the reference current and the memory cell current during the first period and generates a second current based on the other of the reference current and the memory cell current during the second period. A sensing stage senses a first value based on the first current and stores the first value during the first period, senses a second value based on the second current during the second period and compares the first value to the second value.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 25, 2010
    Assignee: Marvell World Trade Ltd.
    Inventors: Pantas Sutardja, Yonghua Song, Bo Wang, Chih-Hsin Wang, Qiang Tang