Patents by Inventor Chih-Hsin Yang
Chih-Hsin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240120288Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a substrate, an encapsulant and an electronic component. The encapsulant is disposed over the substrate, and has a first top surface, a second top surface and a first lateral surface extending between the first top surface and the second top surface. A roughness of the first lateral surface is less than or equal to a roughness of the second top surface. The electronic component is disposed over the second top surface of the encapsulant and electrically connected to the substrate.Type: ApplicationFiled: October 7, 2022Publication date: April 11, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Hsin LAI, Chih-Cheng LEE, Shao-Lun YANG, Wei-Chih CHO
-
Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
-
Publication number: 20240084445Abstract: A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.Type: ApplicationFiled: January 4, 2023Publication date: March 14, 2024Inventors: Chih-Wei Chou, Yuan-Hsin Chi, Chih-Hao Yang, Hung-Chih Wang, Yu-Chi Liu, Sheng-Yuan Lin
-
Publication number: 20240071956Abstract: Semiconductor structures and methods for forming the same are provided. A method according to the present disclosure includes forming active regions on a substrate, forming an interconnect structure over the active regions, the interconnect structure including a plurality of dielectric layers and a guard ring disposed within the dielectric layers, etching an opening through the interconnect structure and at least a first portion of the active regions, the opening extending into the substrate, and forming a via structure within the opening. The via structure is surrounded by the guard ring when viewed along a direction perpendicular to a top surface of the substrate.Type: ApplicationFiled: April 21, 2023Publication date: February 29, 2024Inventors: Chih Hsin YANG, Yen Lian LAI, Dian-Hau CHEN, Mao-Nan WANG
-
Publication number: 20230395586Abstract: A semiconductor structure and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a first die having a front surface and a back surface and a second die bonded to the back surface of the first die. The first die includes a plurality of trenches adjacent the back surface and the plurality of trenches are filled with a liquid.Type: ApplicationFiled: June 2, 2022Publication date: December 7, 2023Inventors: Tsung-Chieh Hsiao, Chih Hsin Yang, Liang-Wei Wang, Dian-Hau Chen
-
Publication number: 20230386940Abstract: A method for forming a semiconductor structure is provided. The method includes forming an interconnect structure, and forming a conductive feature electrically connected to the interconnect structure. The method also includes forming a first passivation layer over the interconnect structure and the conductive feature, and etching the first passivation layer to form an opening that exposes the conductive feature. The method further includes performing an electrical test on the conductive feature, filling the opening with an oxide material, and attaching a carrier substrate over the oxide material using a bonding layer.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsin Yang, Dian-Hau Chen, Yen-Ming Chen
-
Publication number: 20230360946Abstract: A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.Type: ApplicationFiled: May 6, 2022Publication date: November 9, 2023Inventors: Chih-Hsin YANG, Dian-Hau CHEN, Yen-Ming CHEN
-
Publication number: 20230101134Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.Type: ApplicationFiled: November 14, 2022Publication date: March 30, 2023Inventors: Chih-Hsin Yang, Yen-Ming Chen, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Dian-Hau Chen
-
Publication number: 20220392897Abstract: Semiconductor structures and fabrication processes are provided. A semiconductor according to the present disclosure includes a first region including a first fin, a second fin, and a third fin extending along a first direction, and a second region abutting the first region. The second region includes a fourth fin and a fifth fin extending along the first direction. The first fin is aligned with the fourth fin and the second fin is aligned with the fifth fin. The third fin terminates at an interface between the first region and the second region.Type: ApplicationFiled: June 30, 2021Publication date: December 8, 2022Inventors: Chih-Hsin Yang, Yen-Ming Chen, Dian-Hau Chen
-
Patent number: 11502182Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.Type: GrantFiled: May 11, 2020Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsin Yang, Yen-Ming Chen, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Dian-Hau Chen
-
Publication number: 20220328759Abstract: In a method of manufacturing a semiconductor device including a magnetic random access memory (MRAM) cell, a first layer made of a conductive material is formed over a substrate. A second layer for a magnetic tunnel junction (MTJ) stack is formed over the first conductive layer. A third layer is formed over the second layer. A first hard mask pattern is formed by patterning the third layer. The MTJ stack is formed by patterning the second layer by an etching operation using the first hard mask pattern as an etching mask. The etching operation stops at the first layer. A sidewall insulating layer is formed over the MTJ stack. After the sidewall insulating layer is formed, a bottom electrode is formed by patterning the first layer to form the MRAM cell including the bottom electrode, the MTj stack and the first hard mask pattern as an upper electrode.Type: ApplicationFiled: September 29, 2021Publication date: October 13, 2022Inventors: Chih-Hsin YANG, Dian-Hau CHEN, Yen-Ming CHEN, Yu-Jen WANG, Chen-Chiu HUANG
-
Publication number: 20210351277Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.Type: ApplicationFiled: May 11, 2020Publication date: November 11, 2021Inventors: Chih-Hsin Yang, Yen-Ming Chen, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Dian-Han Chen
-
Patent number: 8767901Abstract: A real-time clock frequency correction device includes: a quartz oscillator outputting an oscillating signal including a plurality of oscillating pulses with a frequency; a control unit setting a first integer, a second integer, a first number corresponding to the first integer, and a second number corresponding to the second integer according to the frequency, wherein the first integer is a minimum integer that is larger than the frequency, and the second integer is a maximum integer that is smaller than the frequency; a multiplexer outputting the first integer for the first number of times and the second integer for the second number times; and a counter, coupled to the multiplexer and the quartz oscillator, for counting the number of oscillating pulses according to one of the first integer and the second integer and thereby outputting a pulse.Type: GrantFiled: March 15, 2013Date of Patent: July 1, 2014Assignee: Cortex Technology CorporationInventor: Chih-Hsin Yang
-
Publication number: 20110224205Abstract: Provided is combined use of an epidermal growth factor receptor tyrosine kinase inhibitor (EGFR-TKI) and curcumin or its analogue in cancer therapy, which reduces side effects resulting from the EGFR-TKI and reduces doses of the EGFR-TKI needed for the therapy, particular in a patient resistant to the treatment with the EGFR-TKI alone.Type: ApplicationFiled: February 11, 2011Publication date: September 15, 2011Applicant: NATIONAL TAIWAN UNIVERSITYInventors: Huei-Wen Chen, Jen-Yi Lee, Pan-Chyr Yang, Sung-Liang Yu, Jian-Wei Chen, Chih-Hsin Yang, Chao-Chi Ho, Kuo-Hsiung Lee, Yufeng Jane Tseng, Gee-Chen Chang