Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.

Abstract: A method of forming electrical contacts between a first level electrode pattern and a second level electrode pattern through an inter-level dielectric is described. The method uses conducting metal pillars. A first level of electrodes is formed on a wafer. Conducting metal pillars are formed over the regions of the first level electrodes where contact is to be made. The conducting metal pillars are formed by depositing a layer of metal and forming the pillars using photolithographic techniques and etching. A layer of inter-level dielectric is then deposited over the conducting metal pillars and planarized thereby exposing the top surface of the pillars.

Abstract: A method for forming a reduced size contact hole over a structure.

Abstract: The present invention is a method to manufacture a reverse crown capacitor. The method includes forming a triple layer silicon oxide/silicon nitride/silicon oxide over a substrate. A first node contact is defined in the triple layer. Spacers of a first node contact are formed. Then, a contact hole in the first node contact is formed to connect to the substrate. A polysilicon layer is deposited to from the plug of the contact hole. A chemical mechanical polishing (CMP) process is performed to remove the silicon nitride layer. Afterwards, a silicon oxide is formed over the substrate. A second node contact is defined and a polysilicon layer is formed on the second node contact to form the bottom plate of a capacitor. Finally, a dielectric film is formed over the bottom plate and a top plate is formed over the dielectric film.

Abstract: An improved method for forming a dynamic random access memory (DRAM) capacitor with increased capacitance includes depositing a first oxide layer over a substrate, and patterning a first photoresist layer on the first oxide layer, thereby defining a node contact area. A node trench is etched in the first oxide layer using the first photoresist as a mask. Afterwards, a polysilicon layer is deposited on the first oxide layer, and a second photoresist layer is patterned on this polysilicon layer, defining an electrode area. A hemispherical-grain (HSG) polysilicon layer is deposited on the polysilicon layer and the first oxide layer. The HSG polysilicon layer is then etched back to form a HSG spacer on the sidewalls of the polysilicon layer, and to form a large number of micro-grooves in the upper portion of the polysilicon layer corresponding to the HSG topography of the HSG polysilicon layer. A nitride layer is then conformally deposited to line the micro-grooves.