Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A wafer storage device is provided. The wafer storage device includes a floor, a ceiling, and one or more walls between the floor and the ceiling to define a wafer storage chamber for storage of one or more wafers. The apparatus includes a particle-attraction object, having a positive charge or a negative charge, in the wafer storage chamber and configured to attract particles in the wafer storage chamber.

Abstract: A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

Abstract: A capacitor for a memory device includes a substrate, a bottom electrode, a dielectric layer, and a top electrode. The bottom electrode includes a first bottom electrode layer and a second bottom electrode layer. The first bottom electrode layer is disposed on the substrate. The first bottom electrode layer has a cup shape. The first bottom electrode layer includes a plurality of titanium nitride layers and a plurality of silicon nitride layers that are stacked alternately. The second bottom electrode layer has a cup shape. The second bottom electrode layer includes titanium nitride. An external surface of the second bottom electrode layer contacts an internal surface of the first bottom electrode layer. The dielectric layer conformally covers an internal surface of the second bottom electrode layer. A top electrode conformally covers the dielectric layer.

Abstract: A wafer container includes a frame, a door and at least a pair of shelves. The frame has opposite sidewalls. The pair of the shelves are respectively disposed and aligned on the opposite sidewalls of the frame. Various methods and devices are provided for holding at least one wafer to the shelves during transport.

Abstract: A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and at opposite sides of the word line, a bit line disposed over and electrically connected to the first source/drain region, and a capacitor disposed over and electrically connected to the second source/drain region. The capacitor includes a bottom electrode, a top electrode, and a capacitor dielectric structure disposed between them. The capacitor dielectric structure includes a first metal oxide layer, a second metal oxide layer disposed over the first metal oxide layer, and a third metal oxide layer disposed over the second metal oxide layer. The first, the second and the third metal oxide layer include materials that are different from each other.

Abstract: The present disclosure provides a method for preparing a memory device. The method includes forming a doped region in a semiconductor substrate, and forming a word line across the doped region such that a first source/drain region and a second source/drain region are formed in the doped region and at opposite sides of the word line. The method also includes forming a bit line over and electrically connected to the first source/drain region, and forming a capacitor over and electrically connected to the second source/drain region. The formation of the capacitor includes forming a bottom electrode, forming a capacitor dielectric structure over the bottom electrode, and forming a top electrode over the capacitor dielectric structure.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A semiconductor device includes a substrate, a gate stack, and an epitaxy structure. The gate stack over the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. At least one of the top and bottom WF metal layers includes dopants, and the top WF metal layer is thicker than the bottom WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structure is over the substrate and adjacent the gate stack.

Abstract: A semiconductor device includes a substrate, a gate stack, and an epitaxy structure. The gate stack over the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. At least one of the top and bottom WF metal layers includes dopants, and the top WF metal layer is thicker than the bottom WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structure is over the substrate and adjacent the gate stack.

Abstract: An apparatus comprises a first port, a second port, a battery, and a power control unit electrically connected to the battery, the first port and the second port. The power control unit is configured to, on the basis of an output from the battery: transmit a first power signal to the first port and transmit a second power signal to the second port; or transmit a third power signal received by the first port to the second port.

Abstract: The present invention illustrates an automatic focusing method. Firstly, through multiple cameras of an image capturing device, a scene is captured, such that multiple images generated corresponding to the cameras are obtained. Then, multiple depth maps are generated according to the images. Next, according to the resolutions of single one or multiple objects in the depth maps, the depth information of the single one or multiple objects in the depth maps can be selected to generate a merged depth map. Then, a target focus distance of the single one object or target focus distances of multiple objects are calculated according to the merged depth map. Next, an actual focus distance of the multi-lenses module associated with the cameras is adjusted according to the target focus distance of the single one object or one of the multiple objects.

Abstract: The disclosure relates to a multi-camera imaging system, and a compensation method for image reconstruction. The main components of the multi-camera imaging system are an image capturing module having a multi-lens module and a multi-sensor module, and a distance adjustment unit automatically adjusting the distance between the multi-lens and multi-sensor modules. Note that the distance adjustment unit conducts compensation performed on the change of the system's focal length caused by temperature in the system. The multi-camera imaging system further includes a position-sensing module which is used to sense a displacement or change of the distance made by the distance adjustment unit. A set of image reconstruction parameters corresponding to the displacement or the change of distance is then provided.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and an interfacial layer formed over the substrate. The semiconductor structure further includes a gate structure formed over the interfacial layer. In addition, the interfacial layer is made of metal germanium oxide, metal silicon oxide, or metal germanium silicon oxide and is in direct contact with a top surface of the substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and an interfacial layer formed over the substrate. The semiconductor structure further includes a gate structure formed over the interfacial layer. In addition, the interfacial layer is made of metal germanium oxide, metal silicon oxide, or metal germanium silicon oxide and is in direct contact with a top surface of the substrate.

Abstract: The disclosure relates to a multi-camera imaging system, and a compensation method for image reconstruction. The main components of the multi-camera imaging system are an image capturing module having a multi-lens module and a multi-sensor module, and a distance adjustment unit automatically adjusting the distance between the multi-lens and multi-sensor modules. Note that the distance adjustment unit conducts compensation performed on the change of the system's focal length caused by temperature in the system. The multi-camera imaging system further includes a position-sensing module which is used to sense a displacement or change of the distance made by the distance adjustment unit. A set of image reconstruction parameters corresponding to the displacement or the change of distance is then provided.

Abstract: A power converting device includes a first substrate, a driving module, and a converting module. The first substrate is inserted into a main plate. The first substrate has a first axial direction and a second axial direction perpendicular to the first axial direction, the second axial direction is perpendicular to the main plate. The driving module is located at one side of the first substrate and electrically connected to the first substrate. The converting module is located at the other side of the first substrate and electrically connected to the driving module. A length of the converting module is substantially equal to a length of the first substrate in the first axial direction, and a width of the converting module is smaller than the length of the first substrate in the first axial direction.