Patents by Inventor Chih-Hsuan CHEN
Chih-Hsuan CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220367728Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
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Publication number: 20220344484Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.Type: ApplicationFiled: December 10, 2021Publication date: October 27, 2022Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Hsuan Chen, Ping-Wei Wang
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Patent number: 11482610Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.Type: GrantFiled: July 17, 2020Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO.Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
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Publication number: 20220293767Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yittrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.Type: ApplicationFiled: May 27, 2022Publication date: September 15, 2022Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Yu-Kuan Lin
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Publication number: 20220262799Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.Type: ApplicationFiled: May 9, 2022Publication date: August 18, 2022Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Lien Jung Hung, Shih-Hao Lin
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Patent number: 11349009Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.Type: GrantFiled: June 15, 2020Date of Patent: May 31, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Yu-Kuan Lin
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Patent number: 11329042Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.Type: GrantFiled: November 8, 2019Date of Patent: May 10, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Lien Jung Hung, Shih-Hao Lin
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Patent number: 11239121Abstract: A method of forming a semiconductor device includes providing a structure that includes a substrate, a first fin and a second fin, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer over the first and second gate structures; etching the dielectric layer, thereby forming a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein the first gate contact opening has a first length that is larger than a second length of the second gate contact opening; and filling the first and second gate contact openings with conductive material, thereby forming a first gate contact engaging the first gate structure and a second gate contact engaging the second gate structure.Type: GrantFiled: September 4, 2020Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsuan Chen, Jui-Lin Chen, Yu-Kuan Lin
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Publication number: 20210391439Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Yu-Kuan Lin
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Publication number: 20210098604Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.Type: ApplicationFiled: July 17, 2020Publication date: April 1, 2021Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
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Publication number: 20210098471Abstract: A method of forming a semiconductor device includes providing a structure that includes a substrate, a first fin and a second fin, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer over the first and second gate structures; etching the dielectric layer, thereby forming a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein the first gate contact opening has a first length that is larger than a second length of the second gate contact opening; and filling the first and second gate contact openings with conductive material, thereby forming a first gate contact engaging the first gate structure and a second gate contact engaging the second gate structure.Type: ApplicationFiled: September 4, 2020Publication date: April 1, 2021Inventors: Chih-Hsuan Chen, Jui-Lin Chen, Yu-Kuan Lin
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Publication number: 20200176447Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.Type: ApplicationFiled: November 8, 2019Publication date: June 4, 2020Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Lien Jung Hung, Shih-Hao Lin
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Patent number: 10286567Abstract: A robot includes a moving mechanism, a sensor device and a control device. The sensor device senses a gesture of a user hand in a sensing zone thereof. The control device causes the moving mechanism to perform an action instruction that corresponds to the gesture when the gesture matches a piece of gesture data in a gesture database thereof.Type: GrantFiled: May 3, 2017Date of Patent: May 14, 2019Assignee: HIWIN TECHNOLOGIES CORP.Inventors: Che-Hsuan Chang, Chih-Hsuan Chen, Po-Chiao Huang, Zong-Sian Jiang
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Publication number: 20180319024Abstract: A robot includes a moving mechanism, a sensor device and a control device. The sensor device senses a gesture of a user hand in a sensing zone thereof. The control device causes the moving mechanism to perform an action instruction that corresponds to the gesture when the gesture matches a piece of gesture data in a gesture database thereof.Type: ApplicationFiled: May 3, 2017Publication date: November 8, 2018Inventors: Che-Hsuan CHANG, Chih-Hsuan CHEN, Po-Chiao HUANG, Zong-Sian JIANG
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Patent number: 9953862Abstract: A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a metal silicide film, with plasma of the fluorine-containing gas (process S101). Then, the plasma processing method performs a reduction process of supplying a hydrogen-containing gas into the plasma processing space and reducing, with plasma of the hydrogen-containing gas, a metal-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process (process S102). Thereafter, the plasma processing method performs a removal process of supplying an oxygen-containing gas into the plasma processing space and removing metal, which is obtained by reducing the metal-containing material in the reduction process, with plasma of the oxygen-containing gas (process S103).Type: GrantFiled: November 4, 2015Date of Patent: April 24, 2018Assignee: TOKYO ELECTRON LIMITEDInventors: Akitoshi Harada, Yen-Ting Lin, Chih-Hsuan Chen, Ju-Chia Hsieh, Shigeru Yoneda
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Publication number: 20170182662Abstract: A robot safety guard system for installation in the ground around a robot with an operating range is disclosed to include a plurality of sensor modules mounted on the ground beyond the operating range of the robot. Each sensor module includes 2 first sensors each providing a first sensing range. The first sensing ranges of the first sensors of the sensor modules are combined to define a first warning area. One of the sensor modules further includes a second sensor that provides a second sensing range. The second sensing range defines a second warning area beyond the first warning area. In this way, the robot safety guard system is constructed having low construction costs, fast reaction time and space-saving.Type: ApplicationFiled: December 2, 2016Publication date: June 29, 2017Inventors: Jiun-Kai HUANG, Po-Chiao HUANG, Chih-Hsuan CHEN, Tsung-Hsien CHIANG
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Publication number: 20160315005Abstract: A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a metal silicide film, with plasma of the fluorine-containing gas (process S101). Then, the plasma processing method performs a reduction process of supplying a hydrogen-containing gas into the plasma processing space and reducing, with plasma of the hydrogen-containing gas, a metal-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process (process S102). Thereafter, the plasma processing method performs a removal process of supplying an oxygen-containing gas into the plasma processing space and removing metal, which is obtained by reducing the metal-containing material in the reduction process, with plasma of the oxygen-containing gas (process S103).Type: ApplicationFiled: November 4, 2015Publication date: October 27, 2016Inventors: Akitoshi Harada, Yen-Ting Lin, Chih-Hsuan Chen, Ju-Chia Hsieh, Shigeru Yoneda
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Patent number: 9209041Abstract: A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a nickel silicide film, with plasma of the fluorine-containing gas (process S101). Then, the plasma processing method performs a reduction process of supplying a hydrogen-containing gas into the plasma processing space and reducing, with plasma of the hydrogen-containing gas, a nickel-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process (process S102). Thereafter, the plasma processing method performs a removal process of supplying an oxygen-containing gas into the plasma processing space and removing nickel, which is obtained by reducing the nickel-containing material in the reduction process, with plasma of the oxygen-containing gas (process S103).Type: GrantFiled: August 27, 2013Date of Patent: December 8, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Akitoshi Harada, Yen-Ting Lin, Chih-Hsuan Chen, Ju-Chia Hsieh, Shigeru Yoneda
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Patent number: 9201462Abstract: A portable computer includes a computer body and a keyboard. The keyboard includes a plurality of keys and a space bar. The space bar includes a base frame, a touch pad, an elastic element and a key switch. The touch pad is elevatably disposed on the base frame, and one surface of the touch pad can provide a cursor of the portable computer. The elastic element is disposed between the base frame and the touch pad, and elastically supports the touch pad. The key switch is disposed on the other surface of the touch pad. When one of the keys is clicked, the computer body disables the touch pad and enables the key switch.Type: GrantFiled: October 2, 2013Date of Patent: December 1, 2015Assignee: QUANTA COMPUTER INC.Inventors: Wen-Hung Tsai, Wan-Li Sung, Mao-Sung Lin, Chien-Fa Huang, Mao-Chen Hsiao, Chih-Hsuan Chen
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Publication number: 20150221522Abstract: A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a nickel silicide film, with plasma of the fluorine-containing gas (process S101). Then, the plasma processing method performs a reduction process of supplying a hydrogen-containing gas into the plasma processing space and reducing, with plasma of the hydrogen-containing gas, a nickel-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process (process S102). Thereafter, the plasma processing method performs a removal process of supplying an oxygen-containing gas into the plasma processing space and removing nickel, which is obtained by reducing the nickel-containing material in the reduction process, with plasma of the oxygen-containing gas (process S103).Type: ApplicationFiled: August 27, 2013Publication date: August 6, 2015Applicant: Tokyo Electron LimitedInventors: Akitoshi Harada, Yen-Ting Lin, Chih-Hsuan Chen, Ju-Chia Hsieh, Shigeru Yoneda