Abstract: An image sensing device includes a germanium sensor within a semiconductor body and a metalens formed in the back side of the semiconductor body. The metalens is structured to focus infrared light on the germanium sensor and may have a lower profile than an equivalent microlens. Optionally, the metalens is combined with a microlens to achieve a desired focal length. The metalens, or the metalens in combination with a microlens, overcomes a manufacturing process limitation on the focal length of the microlens, which in turn eliminates the need for, or reduces the thickness of, a spacer between the microlens and the germanium sensor. Eliminating the spacer or reducing its thickness improves the angular response of the image sensing device.

Abstract: An operation method performed by an image processor is provided, including the following operations: receiving a mixed image including an input image and a first on-screen-display (OSD) pattern; generating a second OSD pattern, different from the first OSD pattern, based on the mixed image. The second OSD pattern encompasses protection regions of the input image, and the protection regions are in close proximity of the first OSD pattern. The method further includes operations of performing image processing to remaining regions, different from the protection regions, of the input image and generating an output image. The output image includes the second OSD pattern and the remaining regions of the input image, being performed by the image processing.

Abstract: A package structure is provided, and includes a first bonding film formed on a first substrate, and a first alignment mark formed in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The package structure includes a second bonding film formed on a second substrate and bonded to the first bonding film, and a second alignment mark formed in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other. In a top view, the first alignment mark is spaced apart from the second alignment mark, and the distance between adjacent first patterns is less than the distance between the first alignment mark and the second alignment mark.

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.

Abstract: An androgen receptor (AR) binding molecule has the structure of Formula (I) shown in the following: wherein E is CH2, G is CH, is OH, NH2, OTf or C?C, X is CF3 or trifluoromethylphenyl, is a single bond, and Y and Z are CH2; or is absent, X is CF3, is a double bond, and Y and Z are CH.

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.

Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.

Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes first, second, and third transistors and a discharge circuit. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a second gate coupled to a power terminal, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power terminal, a third drain coupled to the first node, and a third source coupled to the ground. The discharge circuit is controlled by a driving voltage at the first node. In response to an electrostatic discharge event occurring on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and the ground according to the driving voltage.

Abstract: A power supply circuit and a power distribution method thereof are provided. The power supply circuit includes a power input switch block, a power supply measurement block, a power supply conversion block and a power supply control block. The power input switch block provides a first power supply voltage to a load circuit based on an external power supply voltage from an adapter. The power supply measurement block measures a current of the first power supply voltage. The power supply conversion block is coupled to the battery module to provide a second power supply voltage to the load circuit. When a battery temperature of the battery module is higher than a critical temperature and a battery power of the battery module is higher than or equal to a critical power, the power supply control block limits the second power supply voltage provided to the load circuit.

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

Abstract: An antenna module disposed on a substrate having a first and a second surface opposite to each other includes a microstrip line, a first radiator, a ground radiator and a ground plane. The microstrip line, the first radiator and the ground radiator are disposed on the first surface. The microstrip line includes a first and a second end opposite to each other. The first end includes a first feeding end. The first radiator is connected to the second end of the microstrip line. The ground radiator surrounds the microstrip line and the first radiator and has a first opening and two opposite grounding ends. The first end of the microstrip line is located in the first opening. A gap is formed between each grounding end and the first feeding end. The ground plane is disposed on the second surface. The ground radiator is connected to the ground plane.

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, an anisotropic layer on the first buffer layer, a second buffer layer on the first buffer layer, and a bulk layer on the anisotropic layer. Preferably, a concentration of boron in the bulk layer is less than a concentration of boron in the anisotropic layer, a concentration of boron in the first buffer layer is less than a concentration of boron in the second buffer layer, and the concentration of boron in the second buffer layer is less than the concentration of boron in the anisotropic layer.

Abstract: An antenna module includes a transceiver chip, a transmitting array antenna, a receiving array antenna, two bandpass filters, and two capacitors. The transmitting array antenna and the receiving array antenna are symmetrically disposed at the two opposite sides of the transceiver chip. One of the bandpass filters is disposed between the transceiver chip and the transmitting array antenna and connected to the transceiver chip and the transmitting array antenna. The other bandpass filter is disposed between the transceiver chip and the receiving array antenna and connected to the transceiver chip and the receiving array antenna. One of the capacitors is disposed between the transmitting array antenna and the corresponding bandpass filter and connected to the transmitting array antenna and the corresponding bandpass filter. The other capacitor is disposed between the receiving array antenna and the corresponding bandpass filter and connected to the receiving array antenna and the corresponding bandpass filter.

Abstract: A pixel array and a pixel unit thereof adapted in a display panel are provided. The pixel array includes a plurality of pixel units, and each pixel unit includes a first gate line, a second gate line, a data line, a first sub-pixel, a second sub-pixel and a third sub-pixel. The first sub-pixel is electrically connected to the second gate line and electrically connected to the data line through the third sub-pixel. The second sub-pixel is electrically connected to the second gate line and the data line. The third sub-pixel is electrically connected to the first gate line and the data line.

Abstract: A pixel array and a pixel unit thereof adapted in a display panel are provided. The pixel array includes a plurality of pixel units, and each pixel unit includes a first gate line, a second gate line, a data line, a first sub-pixel, a second sub-pixel and a third sub-pixel. The first sub-pixel is electrically connected to the second gate line and electrically connected to the data line through the third sub-pixel. The second sub-pixel is electrically connected to the second gate line and the data line. The third sub-pixel is electrically connected to the first gate line and the data line.