Abstract: A dual ion filter is arranged between upper and lower chambers of a substrate processing system. The dual ion filter includes upper and lower filters. The upper filter includes a first plurality of through holes configured to filter ions from a plasma in the upper chamber. The lower filter includes a second plurality of through holes configured to control plasma uniformity in the lower chamber. A diameter of the first plurality of through holes of the upper filter is less than a diameter of the second plurality of through holes of the lower filter. A number of the first plurality of through holes of the upper filter is greater than a number of the second plurality of through holes of the lower filter.

Abstract: Embodiments of the present disclosure generally relate to methods and processes for selectively depositing a metal fill layer into a feature on the surface of a semiconductor structure. In some embodiments, a method of forming a contact structure includes performing a preclean operation on a contact structure to form a precleaned contact structure. The contact structure includes a silicon-based portion exposed in a cavity of a substrate. The method further includes depositing a metal layer over the precleaned contact structure to form a deposited contact structure. The method further includes introducing a metal halide precursor to the deposited contact structure to at least partially remove the second layer from the deposited contact structure to form an etched contact structure. The method further includes depositing a metal fill layer onto the first layer to form a filled contact structure. The deposited metal fill layer comprises a super conformal profile.

Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

Abstract: An electronic package and a heat dissipation structure thereof are provided, in which a supporting member of the heat dissipation structure is disposed around an outer periphery of a central area and has grooves at corner areas. In this way, the grooves can avoid stress concentration in the corner areas, and the rest of the supporting member can well connect and fix the heat dissipation structure and a carrying structure, so as to suppress warpage of the entire electronic package and prevent delamination.

Abstract: An electronic package and a heat dissipation structure thereof are provided, in which supporting members of the heat dissipation structure are arranged in edge areas, and no supporting member is arranged in corner areas. In this way, the supporting members are interrupted at the corner areas, so that stress can be prevented from concentrating in the corner areas, and the entire electronic package can be prevented from warping and delamination.

Abstract: Embodiments of the disclosure include a method of forming contact structure on a semiconductor substrate. The method includes treating a native oxide layer formed on a contact junction, wherein treating the native oxide layer forms a silica salt layer on the contact junction disposed within a contact feature that includes one or more surfaces that comprise silicon nitride. Then exposing the silica salt layer and the one or more surfaces to a plasma comprising oxygen, wherein the plasma forms a silicon oxynitride material on the one or more surfaces. Then removing the second silica salt layer, selectively forming a metal silicide layer on the contact junction, and then filling the contact feature with a metal, wherein filling the feature comprises selectively depositing a metal layer over the selectively formed metal silicide layer.

Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.

Abstract: A dual ion filter is arranged between upper and lower chambers of a substrate processing system. The dual ion filter includes upper and lower filters. The upper filter includes a first plurality of through holes configured to filter ions from a plasma in the upper chamber. The lower filter includes a second plurality of through holes configured to control plasma uniformity in the lower chamber. A diameter of the first plurality of through holes of the upper filter is less than a diameter of the second plurality of through holes of the lower filter. A number of the first plurality of through holes of the upper filter is greater than a number of the second plurality of through holes of the lower filter.

Abstract: Processing chambers including at least one gas reservoir connected to and in fluid communication with the lid through a fast-switching valve and a gas reservoir line are described. Processing methods, for example, etching methods, using the processing chambers are also described.

Abstract: A substrate processing system includes an upper chamber and a gas delivery system to supply a gas mixture to the upper chamber. An RF generator generates plasma in the upper chamber. A lower chamber includes a substrate support. A dual ion filter is arranged between the upper chamber and the lower chamber. The dual ion filter includes an upper filter including a first plurality of through holes configured to filter ions. A lower filter includes a second plurality of through holes configured to control plasma uniformity.

Abstract: A method of forming a semiconductor device structure includes forming a nucleation layer within at least one feature. The method includes exposing the nucleation layer to a nitrogen plasma treatment. The nitrogen plasma treatment preferentially treats the top field and sidewalls while leaving the bottom surface substantially untreated to encourage bottom up metal growth.

Abstract: A method and apparatus for tungsten gap-fill in semiconductor devices are provided. The method includes performing a gradient oxidation process to oxidize exposed portions of a liner layer, wherein the gradient oxidation process preferentially oxidizes an overhang portion of the liner layer, which obstructs or blocks top openings of one or more features formed within a field region of a substrate. The method further includes performing an etchback process to remove or reduce the oxidized overhang portion of the liner layer, exposing the liner layer to a chemical vapor transport (CVT) process to remove metal oxide remaining from the gradient oxidation process and the etchback process, and performing a tungsten gap-fill process to fill or partially fill the one or more features.

Abstract: A transmitter includes a pre-driver stage circuitry, a post-driver stage circuitry, and resistance adjustment circuits. The pre-driver stage circuitry is configured to output a second data signal according to a first data signal. The post-driver stage circuitry is configured to output a third data signal according to the second data signal. The resistance adjustment circuits are configured to provide a first variable resistor and a second variable resistor, and transmit a first power supply voltage and a second power supply voltage to at least one of the pre-driver stage circuitry or the post-driver stage circuitry, in order to adjust a slew rate of the third data signal.

Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on exposed top surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in the top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes the oxidized portion of the seed layer. A second etch process removes portions of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.

Abstract: A method of performing pulsed remote plasma etching includes arranging a substrate in a processing chamber configured to perform pulsed remote plasma etching, setting at least one process parameter of the processing chamber, supplying at least one gas mixture to an upper chamber region of the processing chamber, supplying, in an ON period, a first voltage to coils arranged around the upper chamber region to energize the at least one gas mixture and generate plasma within the upper chamber region of the processing chamber, turning off the first voltage in an OFF period to discontinue generating plasma within the upper chamber region of the processing chamber, and alternating between supplying the first voltage in the ON period and turning off the first voltage in the OFF period to generate pulsed remote plasma within the upper chamber region of the processing chamber.