Abstract: In an embodiment, a package includes an integrated circuit device attached to a substrate; an encapsulant disposed over the substrate and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with the top surface of the integrated circuit device; and a heat dissipation structure disposed over the integrated circuit device and the encapsulant, wherein the heat dissipation structure includes a spreading layer disposed over the encapsulant and the integrated circuit device, wherein the spreading layer includes a plurality of islands, wherein at least a portion of the islands are arranged as lines extending in a first direction in a plan view; a plurality of pillars disposed over the islands of the spreading layer; and nanostructures disposed over the pillars.

Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.

Abstract: An antenna apparatus includes a feeding antenna inside an electronic device and one or more antenna elements, such as a floating metal antenna, disposed on a rear cover of the electronic device. The floating metal antenna and a feeding antenna inside the electronic device may form a coupling antenna structure. The feeding antenna may be an antenna fastened on an antenna support (which may be referred to as a support antenna). The feeding antenna may alternatively be a slot antenna formed by slitting on a metal middle frame of the electronic device. The antenna apparatus may be implemented in limited design space, thereby effectively saving antenna design space inside the electronic device. The antenna apparatus may generate excitation of a plurality of resonance modes, so that antenna bandwidth and radiation characteristics can be improved.

Abstract: A high voltage metal oxide semiconductor device including a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

Abstract: An LDMOS transistor includes a substrate having first conductive type, a first well having second conductive type, an isolation structure disposed on the substrate, and a deep doped region having first conductive type disposed between the first well and the substrate. The deep doped region is heavily doped, a portion of the deep doped region is disposed in the bottom portion of the first well, and the other portion of the deep doped region is disposed in the substrate.

Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

Abstract: A high voltage metal oxide semiconductor device including a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

Abstract: A waste gas treating device includes two cleansing towers, a plurality of ceramic (or porcelain) balls fully filled in the two towers, and a specific liquid filled in the two towers for waste gas pumped in firstly in the first tower to flow upward through gaps among the ceramic balls and contact with the liquid. Then toxic substances in waste gas react with the liquid to produce byproducts, which sink down out of the first tower and then into a sediment pool. Partial waste gas flowing up to a top end of the first tower is pumped into the second tower for cleansing once again in the same process in the first one to let waste gas cleansed completely and flow out of an upper end of the second tower into atmosphere.

Abstract: A method of fabricating a MOS sensor is described. A P-doped region extending into a substrate is formed. A stacked polysilicon structure is formed over the P-doped region. Ions are implanted into the substrate to form an N-doped region extending shallowly into the P-doped region, the stacked polysilicon structure serving as an implantation buffer layer. The stacked polysilicon structure are patterned and etched to form a stacked polysilicon ring over the N-doped region. A metal line is formed for electrically connecting the stacked polysilicon ring with a gate of a MOS transistor.

Abstract: A method of fabricating a MOS sensor is described. A P-doped region extending into a substrate is formed. A stacked polysilicon structure is formed over the P-doped region. Ions are implanted into the substrate to form an N-doped region extending shallowly into the P-doped region, the stacked polysilicon structure serving as an implantation buffer layer. The stacked polysilicon structure are patterned and etched to form a stacked polysilicon ring over the N-doped region. A metal line is formed for electrically connecting the stacked polysilicon ring with a gate of a MOS transistor.

Abstract: A CMOS sensor. The CMOS sensor comprises a substrate, a gate electrode formed on the substrate, a source/drain region formed in the substrate on one side of the gate electrode, and a sensor region formed in the substrate on another side of the gate electrode. The impurity in the source/drain region is arsenic. The source/drain further comprises a lightly doped drain region. The sensor region comprises a first doped region and a second doped region which together have a dentoid profile. The impurity in the first doped region and the second doped region is phosphorus.

Abstract: A CMOS sensor. The CMOS sensor comprises a substrate, a gate electrode formed on the substrate, a source/drain region formed in the substrate on one side of the gate electrode, and a sensor region formed in the substrate on another side of the gate electrode. The impurity in the source/drain region is arsenic. The source/drain further comprises a lightly doped drain region. The sensor region comprises a first doped region and a second doped region which together have a dentoid profile. The impurity in the first doped region and the second doped region is phosphorus.

Abstract: A method of forming a CMOS sensor. Shallow first doped regions are formed in a provided substrate beside a gate electrode which is on the substrate. One of the shallow first doped region is defined as a source/drain area. Another of the shallow first doped region is defined as a sensor area. A spacer is formed on the sidewall of the gate electrode. A second doped region is formed within the predetermined sensor area by implanting. In the predetermined sensor area, the second doped region is deeper than the first doped region. The sensor region is composed of the first doped region and the second doped region.

Abstract: A method for increasing isolation ability is disclosed. A shallow trench into semiconductor device is formed on a wafer. Therefore the wafer owns a semiconductor substrate and wherein a first gate oxide layer is formed on the semiconductor substrate. A nitride layer is formed on the gate oxide layer. Then the method will include the following statement. Firstly a deep well layer is formed into the semiconductor substrate. Then patterning oxide layer and the nitride layer is carried out. Thereafter trenches is formed. The portion of silicon nitride layer and gate oxide layer will be etched according to the pattern of the gate oxide layer and the nitride layer. Sequentially first implanting a couple of device cell into the deep well of semiconductor substrate is achieved. Then the couple of device cell is annealed. The whole silicon nitride layer is removed. Not only the second implanting cell device will be obtained but also the third implanting cell device will be achieved.