Patents by Inventor Chih-Hua Liu

Chih-Hua Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250067271
    Abstract: A ventilation system comprises a ventilation fan with a lamp for installing to a ceiling having an installation opening. The ventilation fan comprises a housing, a fan module, a power box, a junction box, a lamp module and a support. The housing has a first opening and an air outlet. The fan module comprises an inlet opening and an outlet opening. The outlet opening communicates with the air outlet. The power box has a first circuit board. The lamp module and the housing are located at opposite sides of the installation opening. The junction box is electrically connected to the first circuit board and the lamp module. The impeller comprises a hub, and a ratio of a height of the hub to a height of the housing is less than 0.5. A ratio of a height of the impeller to a height of the housing is greater than 0.65.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: YU-HSIANG HUANG, YUAN-CHUAN LIU, CHIH-HUA LIN
  • Patent number: 12230597
    Abstract: A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Chih-Chiang Tsao, Wei-Yu Chen, Hsiu-Jen Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20250053103
    Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Shao-Hua WANG, Kueilin HO, Cheng Wei SUN, Zong-You YANG, Chih-Chun CHIANG, Yi-Fam SHIU, Chueh-Chi KUO, Heng-Hsin LIU, Li-Jui CHEN
  • Patent number: 12222545
    Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Chung-Ming Weng, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11107917
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first doped well, a second doped well, a mixed doped well, and a gate structure. The first, the second, and the mixed doped wells are disposed in the semiconductor substrate. At least a part of the first doped well and at least a part of the second doped well are located at two opposites sides of the gate structure in a horizontal direction respectively. The mixed doped well are located between the first doped well and the second doped well. The first and the second doped well include a first conductivity type dopant and a second conductivity type dopant respectively. The mixed doped well includes a mixed dopant. A part of the mixed dopant is identical to the first conductivity type dopant, and another part of the mixed dopant is identical to the second conductivity type dopant.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: August 31, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: I-Jhen Hsu, Chih-Hua Liu, Kai-Yi Huang, Ta-Hsun Yeh
  • Publication number: 20210083109
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first doped well, a second doped well, a mixed doped well, and a gate structure. The first, the second, and the mixed doped wells are disposed in the semiconductor substrate. At least a part of the first doped well and at least a part of the second doped well are located at two opposites sides of the gate structure in a horizontal direction respectively. The mixed doped well are located between the first doped well and the second doped well. The first and the second doped well include a first conductivity type dopant and a second conductivity type dopant respectively. The mixed doped well includes a mixed dopant. A part of the mixed dopant is identical to the first conductivity type dopant, and another part of the mixed dopant is identical to the second conductivity type dopant.
    Type: Application
    Filed: January 16, 2020
    Publication date: March 18, 2021
    Inventors: I-Jhen Hsu, Chih-Hua Liu, Kai-Yi Huang, Ta-Hsun Yeh
  • Patent number: 10818429
    Abstract: An inductor device includes at least two wires and at least two switches. Each of the at least two wires includes an opening, and the openings are disposed correspondingly to each other. One of the at least two switches is coupled to two terminals of the opening of one of the at least two wires. Another one of the at least two switches is coupled to one terminal of the opening of the one of the at least two wires and one terminal of the opening of another one of the at least two wires in an interlaced manner. If the one of the at least two switches is turned on, one of the at least two wires forms an inductor; if another one of the at least two switches is turned on, both of the at least two wires form the inductor.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: October 27, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Chih-Hua Liu
  • Patent number: 10369827
    Abstract: A transfer film including a substrate, a protection layer, a metal coating layer, and an ink layer is provided. The substrate has a first surface and a second surface, and the first surface has a first stereoscopic pattern. The protection layer is disposed on the substrate, and has a third surface and a fourth surface. The third surface contacts the first surface, and has a second stereoscopic pattern complementing the first stereoscopic pattern. The fourth surface has a third stereoscopic pattern. The metal coating layer is disposed on the protection layer, and has a fifth surface contacting the fourth surface and a sixth surface. The ink layer is disposed on the metal coating layer. The protection layer and the substrate are separated after transfer to expose the second stereoscopic pattern and reflect out the third stereoscopic pattern. A manufacturing method of the transfer film is also provided.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: August 6, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Ju-Chen Chiu, Po-An Lin, Chih-Hua Liu
  • Publication number: 20190054750
    Abstract: A transfer film including a substrate, a protection layer, a metal coating layer, and an ink layer is provided. The substrate has a first surface and a second surface, and the first surface has a first stereoscopic pattern. The protection layer is disposed on the substrate, and has a third surface and a fourth surface. The third surface contacts the first surface, and has a second stereoscopic pattern complementing the first stereoscopic pattern. The fourth surface has a third stereoscopic pattern. The metal coating layer is disposed on the protection layer, and has a fifth surface contacting the fourth surface and a sixth surface. The ink layer is disposed on the metal coating layer. The protection layer and the substrate are separated after transfer to expose the second stereoscopic pattern and reflect out the third stereoscopic pattern. A manufacturing method of the transfer film is also provided.
    Type: Application
    Filed: October 11, 2017
    Publication date: February 21, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ju-Chen Chiu, Po-An Lin, Chih-Hua Liu
  • Publication number: 20190035544
    Abstract: An inductor device includes at least two wires and at least two switches. Each of the at least two wires includes an opening, and the openings are disposed correspondingly to each other. One of the at least two switches is coupled to two terminals of the opening of one of the at least two wires. Another one of the at least two switches is coupled to one terminal of the opening of the one of the at least two wires and one terminal of the opening of another one of the at least two wires in an interlaced manner. If the one of the at least two switches is turned on, one of the at least two wires forms an inductor; if another one of the at least two switches is turned on, both of the at least two wires form the inductor.
    Type: Application
    Filed: January 11, 2018
    Publication date: January 31, 2019
    Inventors: Hsiao-Tsung YEN, Chih-Hua LIU
  • Publication number: 20180264873
    Abstract: A decorative film structure includes a foamed resin layer and a protective resin layer. The protective resin layer is disposed on the foamed resin layer and has a stereoscopic patterned surface relatively far from the foamed resin layer. A manufacturing method of the decorative film structure is also provided.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 20, 2018
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ju-Chen Chiu, Po-An Lin, Sheng-Hung Lee, Kuo-Nan Ling, Chih-Hua Liu
  • Patent number: 9242505
    Abstract: A production method of workpiece is provided. First, an adhesive layer is applied on a workpiece, wherein a material of the adhesive layer includes thermosetting resin and radiationcurable resin. The adhesive layer is impressed by a mold, so that the adhesive layer forms a three-dimensional pattern. A first curing process is performed on the adhesive layer by one of radiation-curing and thermal-curing. The workpiece is punched after the first curing process is performed on the adhesive layer, so that the workpiece forms a three-dimensional workpiece. A second curing process is performed on the adhesive layer by another one of radiation-curing and thermal-curing after the workpiece is punched. In addition, a workpiece with three-dimensional pattern is also provided.
    Type: Grant
    Filed: November 24, 2011
    Date of Patent: January 26, 2016
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wan-Li Chuang, Chien-Min Chang, Ju-Chen Chiu, Chih-Hua Liu, Tsung-Sheng Chuang
  • Patent number: 8911581
    Abstract: A composite light guide plate manufacturing method includes the steps of providing a light guide substrate; providing a transfer membrane, which sequentially includes a substrate, a reflective layer and a diffusion microstructure; attaching the transfer membrane to the light guide substrate with a side of the transfer membrane, which has the diffusion microstructure thereon; and removing the substrate to expose the reflective layer.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: December 16, 2014
    Assignee: Compal Electronics, Inc.
    Inventors: Ju-Chen Chiu, Chien-Min Chang, Po-An Lin, Chih-Hua Liu, Hao-Ying Chang
  • Publication number: 20140116607
    Abstract: A composite light guide plate manufacturing method includes the steps of providing a light guide substrate; providing a transfer membrane, which sequentially includes a substrate, a reflective layer and a diffusion microstructure; attaching the transfer membrane to the light guide substrate with a side of the transfer membrane, which has the diffusion microstructure thereon; and removing the substrate to expose the reflective layer.
    Type: Application
    Filed: June 11, 2013
    Publication date: May 1, 2014
    Inventors: Ju-Chen CHIU, Chien-Min CHANG, Po-An LIN, Chih-Hua LIU, Hao-Ying CHANG
  • Publication number: 20120070639
    Abstract: A production method of workpiece is provided. First, an adhesive layer is applied on a workpiece, wherein a material of the adhesive layer includes thermosetting resin and radiationcurable resin. The adhesive layer is impressed by a mold, so that the adhesive layer forms a three-dimensional pattern. A first curing process is performed on the adhesive layer by one of radiation-curing and thermal-curing. The workpiece is punched after the first curing process is performed on the adhesive layer, so that the workpiece forms a three-dimensional workpiece. A second curing process is performed on the adhesive layer by another one of radiation-curing and thermal-curing after the workpiece is punched. In addition, a workpiece with three-dimensional pattern is also provided.
    Type: Application
    Filed: November 24, 2011
    Publication date: March 22, 2012
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wan-Li Chuang, Chien-Min Chang, Ju-Chen Chiu, Chih-Hua Liu, Tsung-Sheng Chuang
  • Patent number: 6621915
    Abstract: The present invention disclosed a method and system inspecting cotton web homogeneity by a digital image processing technique, in particular, for an on-line cotton web homogeneity test. It uses optical principles in conjunction with a charge coupled device type camera to find a theoretical equation indicating the correlation between the transmittance of cotton webs and basic weights (weights per unit area). Next, the invention makes use of a numerical analysis method to find the optimal approximation equation representing a relationship between measured transmittance and basic weights of cotton webs. When executing an on-line inspection, a system according to the invention detects the transmittance of cotton webs by means of the computer controlled visual device and then calculates correlated data of cotton web homogeneity variations according to the approximation equation acquired previously.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: September 16, 2003
    Assignee: China Textile Institute
    Inventors: Hung-Jen Chen, Hsin-Chung Lien, Chih-Hua Liu, Ding-Kuo Huang