Abstract: A transient voltage suppressor with adjustable trigger and holding voltages is provided, including a heavily doped substrate of a first conductivity type connected to a first node, a lightly doped epitaxial layer of a second conductivity type on the substrate, a first and third well region of the first conductivity type, a second well region of the second conductivity type, a first and third heavily doped region of the second conductivity type and a second heavily doped region of the first conductivity type. The heavily doped regions are commonly electrically connected to a second node, and individually disposed in the well regions. Trenches are disposed opposite in the substrate for electrical isolation. A floating base bipolar junction transistor and silicon controlled rectifier can be respectively formed under a positive and negative surged mode. Accordingly, the invention is advantageous of superior electrical performances, high layout flexibility and low area consumption.

Abstract: An end cap for a carriage of a linear guide. The end cap has a closed lubrication port which is openable by operatively connecting a lubrication fitting to the lubrication port. The is formed by injection molding and the closed lubrication port of the end cap is formed by rotary demolding.

Abstract: A composite connector incudes a connector, a carrier circuit board, and a plurality of filtering units. The connector is disposed on at least one surface of the carrier circuit board, and multiple connection pins are disposed on at least one surface of the carrier circuit board. The carrier circuit board is disposed on a main circuit board or a main circuit board connector of the main circuit board. The filtering units are disposed on the carrier circuit board and connected to part or all of the connection pins to filter out noise on the connection pins. The composite connector of the invention can have a filtering function, thereby reducing the manufacturing cost of electronic devices and increasing the routing flexibility of the main circuit board.

Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a first electrode over a substrate. A data storage layer is formed on the first electrode. A conductive layer is formed on the data storage layer. A buffer layer is formed on the conductive layer. The buffer layer comprises a first material. A second electrode is formed on the buffer layer. The second electrode comprises a second material different from the first material.

Abstract: A bipolar junction transistor with adjustable gain is provided, including a semiconductor substrate and doped layer of a first conductivity type, a doped well region of a second conductivity type and a plurality of heavily doped regions. At least one detection circuit is provided with an input voltage and operable to generate an output voltage for a conducting layer to receive, such that current paths generated in the transistor can be determined when the input voltage varies under different operating conditions, including a normal operating mode, a positive and a negative surged operating mode. When a transient event takes place, the bipolar junction transistor is characterized by having a higher gain than it is operating in the normal mode. The proposed invention achieves in integrating the unidirectional and bidirectional electrical characteristics in the disclosed bipolar junction transistor structure by employing the detection circuit such that adjustable gain is obtained.

Abstract: A dielectric isolation layer having a planar top surface is formed over a substrate. A first electrode and a second electrode are formed over the planar top surface. An insulating matrix layer is formed around the first electrode and the second electrode. A phase change material (PCM) line is formed over the insulating matrix layer. A first end portion of the PCM line contacts a top surface of the first electrode and a second end portion of the PCM line contacts a top surface of the second electrode. A dielectric encapsulation layer is formed on sidewalls of the PCM line and over the PCM line and over a top surface of the insulating matrix layer. A heater line is formed prior to, or after, formation of the PCM line. The heater line underlies the PCM line or overlies the PCM line. A PCM switch device may be provided.

Abstract: Inner spacers between a source/drain region of a nanostructure transistor and sacrificial nanostructure layers of the nanostructure transistor are removed prior to formation of a gate structure of the nanostructure transistor. The sacrificial nanostructure layers are removed, and then the inner spacers are removed. The sacrificial nanostructure layers are then replaced with the gate structure of the nanostructure transistor such that the gate structure and the source/drain region are spaced apart by air gaps that result from the removal of the inner spacers. The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.

Abstract: A tool-free unlocking device includes a frame with an opening; an unlatching member movably connected to the frame; and a locking member having a first section fixed on the frame and a second section extending from first section and corresponding to the opening. Thus, when the unlatching member is not pushed, the end surface of the second section of the locking member abuts to form a locked state, or when the unlatching member is pushed from the first section of the locking member to the second section of the locking member, the second section of the locking member will be pushed down to the opening of the frame to form an unlocked state.

Abstract: A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.

Abstract: A joint structure of a telescopic cylinder includes a telescopic unit, an extension unit and a first fixing unit. The telescopic unit includes a first main body, a first combined structure and at least one first fixing structure. The extension unit includes a second main body, a second combined structure and at least one second fixing structure. The first combined structure is screwed to the second combined structure. The first fixing unit includes at least one first fixing body, and the first fixing body is simultaneously arranged in the first fixing structure and the second fixing structure and interferes with the first main body and the second main body so as to prevent the first combined structure and the second combined structure from spiral movement.

Abstract: A method for manufacturing a semiconductor device includes: forming a first dielectric layer on a semiconductor substrate; forming a plurality of spaced-apart electrodes in the first dielectric layer; forming a patterned stack on the electrodes opposite to the semiconductor substrate, the patterned stack including a plurality of stack portions spaced apart from each other, each of the stack portions including a heater portion disposed on and connected to at least one of the electrodes and a phase change material portion disposed on the heater portion opposite to the at least one of the electrodes; forming a second dielectric layer to conformally cover the patterned stack; and forming a third dielectric layer on the second dielectric layer, the third dielectric layer being formed with a plurality of air gaps such that the stack portions are spaced apart from each other by the air gaps.

Abstract: A semiconductor device includes a semiconductor substrate and a spatial light modulator. The spatial light modulator is disposed on the semiconductor substrate, and includes a plurality of pixels. Each of the pixels includes a heater portion, a phase change material portion, and a pair of spacers. The phase change material portion is disposed on the heater portion opposite to the semiconductor substrate. The spacers are disposed on the heater portion and laterally cover the phase change material portion.

Abstract: Method and apparatus for fraud detection are provided. Sensor data from one or more acoustic wave sensors is received, where the one or more acoustic wave sensors transmit acoustic waves towards a set of items within a receptacle and receive reflected acoustic waves from the set of items. A model for the set of items within the receptacle is generated based on the sensor data. One or more features for the set of items are identified by analyzing the model. Checkout data is retrieved from one or more checkout devices. The one or more features for the set of items identified from the model are compared with the checkout data. An alert is generated upon detecting a discrepancy between the one or more features and the checkout data.

Abstract: Various embodiments of the present disclosure are directed towards methods for forming conductive lines and conductive sockets using mandrels with turns, as well as the resulting conductive lines and sockets. A conductive socket of the present disclosure may have a top layout with at least one turn and with a width that is substantially the same as that of conductive lines along the at least one turn. Such a top layout may reduce loading during formation of the conductive socket. Conductive lines of the present disclosure may comprise outer conductive lines and inner conductive lines having ends laterally offset from ends of the outer conductive lines along lengths of the conductive lines. Formation of the inner and outer conductive lines using a mandrel with a turn may enlarge a process window while cutting ends of a sidewall spacer structure from which the inner and outer conductive lines are formed.

Abstract: A device and method of forming a device are provided. The method includes forming a stack of nanostructure channels over a substrate by forming a source/drain opening. The method also includes forming a sacrificial source/drain in the source/drain opening. The method further includes increasing tensile strain of the stack of nanostructure channels by replacing the sacrificial source/drain with a replacement source/drain having germanium concentration that exceeds that of the sacrificial source/drain.

Abstract: A circuit board module capable of suppressing common mode noise includes a circuit board, and a first circuit and a second circuit that are disposed on the circuit board. The circuit board includes an insulating substrate, and a plurality of metal layers. The metal layers are disposed in the insulating substrate, are spaced apart from each other, and include a first metal layer and a second metal layer. The metal layers are formed to include a plurality of conducting lines. The conducting lines cooperatively form a common mode choke structure in which the conducting lines extend in a spiral pattern, so that each of the conducting lines has a spiral winding segment in the spiral pattern. In the spiral pattern, a mutual inductance coupling coefficient between the spiral winding segments of two adjacent ones of the conducting lines is greater than 0.3.

Abstract: A method for fabricating a semiconductor device is disclosed. The method involves forming a stack of alternating semiconductor channels and interposers on a substrate, with sacrificial structures between the interposers. Source/drain openings are formed, and strain in the channels is modified. Source/drain structures are formed in the openings, and dielectric layers are deposited. The resulting device features stacked nanostructures with inner spacers of varying heights, enabling improved performance in electronic devices.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A data processing method for a DNN model includes: reading weights of transmission data; quantizing each weight into bits sequentially including first, second, third, and fourth-type bits; sequentially interleaving the first-type bit into a first bit set; sequentially interleaving each second-type bit into second bit sets and reading a second compression rate of each second bit set in response to the compressible second bit sets; interleaving the third-type bit into a third bit set and reading a third compression rate of the third bit set in response to the compressible third bit set; compressing each second bit set with the second compression rate, and compressing the third bit set with the third compression rate; sequentially coding the first bit set, each compressed second bit set, and the compressed third bit set to generate first encoded data corresponding to the transmission data; transmitting the first encoded data to an external device.