Patents by Inventor Chih-Huang Lin

Chih-Huang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113034
    Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 4, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Chih-Hao YU, PaoTai HUANG, Pei-Hsuan LO, Shih-Peng TAI
  • Patent number: 10176129
    Abstract: A control method for a first device of an inter-integrated circuit (I2C) system including a microcontroller unit (MCU), includes receiving a first indication from the MCU of the I2C system, wherein the first indication configures the first device from a slave mode to a master mode; polling the first device itself for status information of the first device when the first device is in the master mode; determining whether the status information of the first device matches a target status after polling; and determining to perform a parameter adjustment on a second device of the I2C system when determining that the status information of the first device matches the target status.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: January 8, 2019
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chih-Huang Lin, Hong-Chu Chen, Min-Hui Chu, Chin-Hui Huang, Wei-Lung Liu, Tai-Yu Chiu, Chao-Chun Huang, Su-Wei Lien
  • Publication number: 20180109227
    Abstract: An amplifier with adjustable gain including a plurality of differential amplifiers and an output stage circuit is provided. Each of the differential amplifiers has at least one differential pair, two current terminals of each of the differential pairs are coupled by a connection structure, and the connection structure provides a negative feedback resistance. The differential amplifiers commonly receive a differential input signal pair, and output terminals of the differential amplifiers are coupled together. The output stage circuit inverts a voltage on the output terminals of the differential amplifiers to generate an output voltage. A direct current gain of the amplifier with adjustable gain is determined by adjusting at least one of working numbers of the differential amplifiers and the differential pairs.
    Type: Application
    Filed: December 21, 2016
    Publication date: April 19, 2018
    Applicant: Faraday Technology Corp.
    Inventor: Chih-Huang Lin
  • Patent number: 9948244
    Abstract: An amplifier with adjustable gain including a plurality of differential amplifiers and an output stage circuit is provided. Each of the differential amplifiers has at least one differential pair, two current terminals of each of the differential pairs are coupled by a connection structure, and the connection structure provides a negative feedback resistance. The differential amplifiers commonly receive a differential input signal pair, and output terminals of the differential amplifiers are coupled together. The output stage circuit inverts a voltage on the output terminals of the differential amplifiers to generate an output voltage. A direct current gain of the amplifier with adjustable gain is determined by adjusting at least one of working numbers of the differential amplifiers and the differential pairs.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 17, 2018
    Assignee: Faraday Technology Corp.
    Inventor: Chih-Huang Lin
  • Publication number: 20170371819
    Abstract: A control method for a first device of an inter-integrated circuit (I2C) system including a microcontroller unit (MCU), includes receiving a first indication from the MCU of the I2C system, wherein the first indication configures the first device from a slave mode to a master mode; polling the first device itself for status information of the first device when the first device is in the master mode; determining whether the status information of the first device matches a target status after polling; and determining to perform a parameter adjustment on a second device of the I2C system when determining that the status information of the first device matches the target status.
    Type: Application
    Filed: July 19, 2016
    Publication date: December 28, 2017
    Inventors: Chih-Huang Lin, Hong-Chu Chen, Min-Hui Chu, Chin-Hui Huang, Wei-Lung Liu, Tai-Yu Chiu, Chao-Chun Huang, Su-Wei Lien
  • Patent number: 9530231
    Abstract: A method for generating masking image using general polygonal mask includes receiving a pixel of a raw image and a polygon vertices array corresponding to a polygonal mask, determining whether the pixel is inside the polygonal mask, labeling the pixel to be a masked pixel if the pixel is inside the polygonal mask, or labeling the pixel to be a visible pixel if the pixel is outside the polygonal mask, and outputting the masked pixel or the visible pixel to generate the masking image.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: December 27, 2016
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Jau-Hong Kao, Shiang-Fei Wang, Yi-Jen Wu, Chih-Huang Lin, Min-Hui Chu, Hong-Chu Chen, Chi-Fan Liou
  • Publication number: 20160260235
    Abstract: A method for generating masking image using general polygonal mask includes receiving a pixel of a raw image and a polygon vertices array corresponding to a polygonal mask, determining whether the pixel is inside the polygonal mask, labeling the pixel to be a masked pixel if the pixel is inside the polygonal mask, or labeling the pixel to be a visible pixel if the pixel is outside the polygonal mask, and outputting the masked pixel or the visible pixel to generate the masking image.
    Type: Application
    Filed: March 5, 2015
    Publication date: September 8, 2016
    Inventors: Jau-Hong Kao, Shiang-Fei Wang, Yi-Jen Wu, Chih-Huang Lin, Min-Hui Chu, Hong-Chu Chen, Chi-Fan Liou
  • Patent number: 6748288
    Abstract: A semiconductor manufacturing execution system (MES) is disclosed, including a memory module, a comparing module, and an outputting module. The memory module stores a basic database and a recipe distribution management (RDM) database. The basic database includes multiple basic records, and the RDM database includes multiple RDM records. The comparing module compares operation data, received from a manufacturing machine, to each of the RDM records, and secondarily to each of the basic records, to determine whether the operation data matches at least one of the RDM and basic records. The outputting module outputs a limiting signal to the manufacturing machine if the operation data matches at least one of the RDM records. The limiting signal prevents the manufacturing machine from executing a process corresponding to the operation data.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: June 8, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Yeaun-Jyh Su, Chen-Chung Yu, Chih-Huang Lin, Chu-Shan Yu
  • Publication number: 20030204281
    Abstract: A semiconductor manufacturing execution system (MES) is disclosed, including a memory module, a comparing module, and an outputting module. The memory module stores a basic database and a recipe distribution management (RDM) database. The basic database includes multiple basic records, and the RDM database includes multiple RDM records. The comparing module compares operation data, received from a manufacturing machine, to each of the RDM records, and secondarily to each of the basic records, to determine whether the operation data matches at least one of the RDM and basic records. The outputting module outputs a limiting signal to the manufacturing machine if the operation data matches at least one of the RDM records. The limiting signal prevents the manufacturing machine from executing a process corresponding to the operation data.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 30, 2003
    Inventors: Yeaun-Jyh Su, Chen-Chung Yu, Chih-Huang Lin, Chu-Shan Yu
  • Publication number: 20030204528
    Abstract: A manufacturing execution system (MES) is disclosed including a first database and a second database. The first database (e.g., a basic database) stores a first set of records, wherein each of the first set of records includes information regarding a routine operation to be performed on at least one semiconductor wafer when the at least one semiconductor wafer is positioned within a process tool. The second database (e.g., a special engineer requirement, or SER, database) stores a second set of records, wherein each of the second set of records includes information regarding a special operation to be performed on the at least one semiconductor wafer when positioned within the process tool. A method is also described, which may be embodied within the MES. The method includes receiving operation data from the process tool, wherein the operation data includes information regarding a selected operation (e.g., a user-selected recipe) to be performed within the process tool.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 30, 2003
    Inventors: Yeaun-Jyh Su, Chen-Chung Yu, Chih-Huang Lin, Chu-Shan Yu