Patents by Inventor Chih-huei Wu
Chih-huei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145481Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: POCHUN WANG, GUO-HUEI WU, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, LI-CHUN TIEN
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Patent number: 11967596Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.Type: GrantFiled: August 5, 2021Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
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Patent number: 11948886Abstract: A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.Type: GrantFiled: April 29, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
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Patent number: 11942420Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.Type: GrantFiled: June 8, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
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Publication number: 20240096866Abstract: An integrated circuit includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail extending in a first direction. A first distance between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance between the long edge of the second power rail and the first alignment boundary of the second-type active zone. Each of the first distance and the second distance is along a second direction which is perpendicular to the first direction.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Guo-Huei WU, Chih-Liang CHEN, Li-Chun TIEN
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Patent number: 11916017Abstract: An integrated circuit includes a plurality of horizontal conducting lines in a first connection layer, a plurality of gate-conductors below the first connection layer, a plurality of terminal-conductors below the first connection layer, and a via-connector directly connecting one of the horizontal conducting lines with one of the gate-conductors or with one of the terminal-conductors. The integrated circuit also includes a plurality of vertical conducting lines in a second connection layer above the first connection layer, and a plurality of pin-connectors for a circuit cell. A first pin-connector is directly connected between a first horizontal conducting line and a first vertical conducting line atop one of the gate-conductors. A second pin-connector is directly connected between a second horizontal conducting line and a second vertical conducting line atop a vertical boundary of the circuit cell.Type: GrantFiled: August 26, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Ling Chang, Chih-Liang Chen, Chia-Tien Wu, Guo-Huei Wu
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Patent number: 9343499Abstract: An integrated circuit system includes a first device and second device wafer. A wafer bonding region is disposed at an interface of a front side of a first dielectric layer of the first device wafer and a front side of a second dielectric layer of the second device wafer such that wafer bonding region bonds the first device wafer to the second device wafer. The wafer bonding region includes dielectric material having a higher silicon concentration than a dielectric material of the first and second dielectric layers of the first and second device wafers. A conductive path couples a first conductor of the first device wafer to a second conductor of the second device wafer. The conductive path is formed in a cavity etched through the wafer bonding region between the first conductor and the second conductor.Type: GrantFiled: April 23, 2015Date of Patent: May 17, 2016Assignee: OmniVision Technologies, Inc.Inventors: Hsin-Neng Tai, Hung-Ming Weng, Michael Chen, Chih-Huei Wu
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Patent number: 8000520Abstract: An image sensor testing apparatus is disclosed. The image sensor testing apparatus includes an electronic test system having a light source for illuminating an image sensor wafer to generate pixel data and a host processor for receiving the pixel data. An interface card coupled to the electronic test system has a programmable processor for processing the pixel data to generate processed data, the processed data transmitted to and analyzed by the host processor together with the pixel data to detect pixel defects in the image sensor wafer.Type: GrantFiled: November 28, 2007Date of Patent: August 16, 2011Assignee: OmniVision Technologies, Inc.Inventors: Chia-Lun Chang, Chih-huei Wu, John T. Yue
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Publication number: 20090135414Abstract: An image sensor testing apparatus is disclosed. The image sensor testing apparatus includes an electronic test system having a light source for illuminating an image sensor wafer to generate pixel data and a host processor for receiving the pixel data. An interface card coupled to the electronic test system has a programmable processor for processing the pixel data to generate processed data, the processed data transmitted to and analyzed by the host processor together with the pixel data to detect pixel defects in the image sensor wafer.Type: ApplicationFiled: November 28, 2007Publication date: May 28, 2009Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Chia-Lun CHANG, Chih-huei WU, John T. YUE
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Patent number: 7368772Abstract: The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.Type: GrantFiled: August 7, 2003Date of Patent: May 6, 2008Assignee: Omnivision Technologies, Inc.Inventors: Xinping He, Chih-huei Wu, Tiemin Zhao
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Patent number: 7105878Abstract: The active pixel includes a photodiode, a reset transistor, and a pixel output transistor. The photodiode is substantially covered with a protective structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. The protective structure has a photodiode contact formed therein to electrically connect the photodiode to the pixel output transistor.Type: GrantFiled: September 20, 2004Date of Patent: September 12, 2006Assignee: OmniVision Technologies, Inc.Inventors: Xinping He, Chih-Huei Wu, Hongli Yang
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Patent number: 7091058Abstract: A method for protecting an image sensor die is disclosed. The method comprises forming a plurality of image sensor die having micro-lenses onto a semiconductor wafer. Then, a protective layer is formed over the image sensor die. After the protective layer has been formed, and without any removal step of the protective layer, the wafer is diced to separate the plurality of image sensor die. Finally, the image sensor die are mounted onto an integrated circuit package and the protective layer is removed.Type: GrantFiled: December 11, 2003Date of Patent: August 15, 2006Assignee: OmniVision Technologies, Inc.Inventors: Chih-huei Wu, Xinping He
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Patent number: 6909162Abstract: A method for reducing dark current in a photodiode is disclosed. The photodiode comprises a N-well formed in a P-substrate. The method comprises doping the surface of said N-well with a nitrogen dopant. Alternatively, an oxygen or silicon dopant may be used. Still alternatively, a silicon oxynitride layer may be formed over the N-well.Type: GrantFiled: November 2, 2001Date of Patent: June 21, 2005Assignee: OmniVision Technologies, Inc.Inventors: Chih-huei Wu, Tiemin Zhao, Xinping He
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Publication number: 20050130337Abstract: A method for protecting an image sensor die is disclosed. The method comprises forming a plurality of image sensor die having micro-lenses onto a semiconductor wafer. Then, a protective layer is formed over the image sensor die. After the protective layer has been formed, and without any removal step of the protective layer, the wafer is diced to separate the plurality of image sensor die. Finally, the image sensor die are mounted onto an integrated circuit package and the protective layer is removed.Type: ApplicationFiled: December 11, 2003Publication date: June 16, 2005Inventors: Chih-Huei Wu, Xinping He
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Publication number: 20050062085Abstract: The active pixel includes a photodiode, a reset transistor, and a pixel output transistor. The photodiode is substantially covered with a protective structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. The protective structure has a photodiode contact formed therein to electrically connect the photodiode to the pixel output transistor.Type: ApplicationFiled: September 20, 2004Publication date: March 24, 2005Inventors: Xinping He, Chih-Huei Wu, Hongli Yang
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Publication number: 20040026724Abstract: The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.Type: ApplicationFiled: August 7, 2003Publication date: February 12, 2004Inventors: Xinping He, Chih-Huei Wu, Tiemin Zhao
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Patent number: 6649950Abstract: The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.Type: GrantFiled: August 14, 2002Date of Patent: November 18, 2003Assignee: OmniVision Technologies, Inc.Inventors: Xinping He, Chih-huei Wu, Tiemin Zhao
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Publication number: 20030086011Abstract: A method for reducing dark current in a photodiode is disclosed. The photodiode comprises a N-well formed in a P-substrate. The method comprises doping the surface of said N-well with a nitrogen dopant. Alternatively, an oxygen or silicon dopant may be used. Still alternatively, a silicon oxynitride layer may be formed over the N-well.Type: ApplicationFiled: November 2, 2001Publication date: May 8, 2003Inventors: Chih-huei Wu, Tiemin Zhao, Xinping He
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Publication number: 20030085400Abstract: The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.Type: ApplicationFiled: August 14, 2002Publication date: May 8, 2003Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Xinping He, Chih-Huei Wu, Tiemin Zhao
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Patent number: 6462365Abstract: The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.Type: GrantFiled: November 6, 2001Date of Patent: October 8, 2002Assignee: OmniVision Technologies, Inc.Inventors: Xinping He, Chih-huei Wu, Tiemin Zhao