Patents by Inventor Chih-Hui Huang

Chih-Hui Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210358740
    Abstract: The present disclosure for wafer bonding, including forming an epitaxial layer on a top surface of a first wafer, forming a sacrificial layer over the epitaxial layer, trimming an edge of the first wafer, removing the sacrificial layer, forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Inventors: YUNG-LUNG LIN, HAU-YI HSIAO, CHIH-HUI HUANG, KUO-HWA TZENG, CHENG-HSIEN CHOU
  • Publication number: 20210320097
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11137581
    Abstract: A wafer-level homogeneous bonding optical structure includes two optical lens sets disposed on an optically transparent wafer and a spacer disposed on the optically transparent wafer and between the two optical lens sets. The spacer is homogeneously bonded to and integrated with the optically transparent wafer in the absence of a heterogeneous adhesive.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 5, 2021
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chih-Sheng Chang, Teng-Te Huang, Shu-Hao Hsu, Jun-Yu Zhan, Jen-Hui Lai
  • Patent number: 11139210
    Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Chih-Hui Huang, Kuo-Ming Wu
  • Patent number: 11121050
    Abstract: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Chih-Wei Wu, Li-Chung Kuo, Long Hua Lee, Sung-Hui Huang, Ying-Ching Shih, Pai Yuan Li
  • Publication number: 20210272941
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 11101260
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11087971
    Abstract: The present disclosure provides a method for wafer bonding, including providing a wafer, forming a sacrificial layer on a top surface of the first wafer, trimming an edge of the first wafer to obtain a first wafer area, cleaning the top surface of the first wafer, removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer having a second wafer area greater than the first wafer area.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Lung Lin, Hau-Yi Hsiao, Chih-Hui Huang, Kuo-Hwa Tzeng, Cheng-Hsien Chou
  • Publication number: 20210233813
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
  • Patent number: 11041242
    Abstract: A gas shower head includes a plate, a plurality of central holes disposed in a central region of the plate, and a plurality of peripheral holes disposed in a peripheral region of the plate. The central holes are configured to form a first portion of a material film, and the peripheral holes are configured to form a second portion of the material film. A hole density in the peripheral region is greater than a hole density in the central region. The first portion of the material film includes a first thickness corresponding to the hole density in central region, and the second portion of the material film includes a second thickness corresponding to the hole density in peripheral region and greater than the first thickness.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Hui Huang, Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Publication number: 20210134663
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: September 30, 2020
    Publication date: May 6, 2021
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Patent number: 10978345
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
  • Patent number: 10879288
    Abstract: Various embodiments of the present application are directed towards an image sensor having a reflector. In some embodiments, the image sensor comprises a substrate, an interlayer dielectric (ILD) structure, an etch stop layer, a wire, and the reflector. The substrate comprises a photodetector. The ILD structure is over the substrate, and the etch stop layer is over the ILD structure. The wire is in the etch stop layer. The reflector is directly over the photodetector and is in the etch stop layer. An upper surface of the wire is elevated above an upper surface of the reflector. By forming the reflector directly over the photodetector, the reflector may reflect radiation that passes through the photodetector without being absorbed back to the photodetector. This gives the photodetector a second chance to absorb the radiation and enhances the quantum efficiency (QE) of the photodetector.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20200321251
    Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Chih-Hui Huang, Kuo-Ming Wu
  • Publication number: 20200312894
    Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.
    Type: Application
    Filed: June 14, 2020
    Publication date: October 1, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Patent number: 10734285
    Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Chih-Hui Huang, Kuo-Ming Wu
  • Patent number: 10727097
    Abstract: The mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. The mechanisms for a hybrid bonding and a integrated system are also provided.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chau Chen, Chih-Hui Huang, Yeur-Luen Tu, Cheng-Ta Wu, Chia-Shiung Tsai, Xiao-Meng Chen
  • Publication number: 20200141004
    Abstract: A gas shower head includes a plate, a plurality of central holes disposed in a central region of the plate, and a plurality of peripheral holes disposed in a peripheral region of the plate. The central holes are configured to form a first portion of a material film, and the peripheral holes are configured to form a second portion of the material film. A hole density in the peripheral region is greater than a hole density in the central region. The first portion of the material film includes a first thickness corresponding to the hole density in central region, and the second portion of the material film includes a second thickness corresponding to the hole density in peripheral region and greater than the first thickness.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: CHIH-HUI HUANG, SHENG-CHAN LI, CHENG-HSIEN CHOU, CHENG-YUAN TSAI
  • Publication number: 20200119081
    Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 16, 2020
    Inventors: Chi-Ming LU, Chih-Hui HUANG, Jung-Chih TSAO, Yao-Hsiang LIANG, Chih-Chang HUANG, Ching-Ho HSU
  • Publication number: 20200105548
    Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen