Abstract: A lifting module for a chassis and an electronic device including the lifting module are provided. The lifting module includes a sidewall bracket, a lifting bracket, a sliding button assembly, and a driven assembly. The sidewall bracket is disposed on a side frame of the chassis. The lifting bracket is movably connected to the sidewall bracket. The sliding button assembly is slidably disposed on the side frame of the chassis. Part of the sliding button assembly is exposed from the chassis. The driven assembly is movably disposed on the sidewall bracket. The driven assembly is connected to interact the sliding button assembly and the lifting bracket. The lifting bracket is driven to move relative to the sidewall bracket selectively by the sliding button assembly through the driven assembly.

Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.

Abstract: A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.

Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.

Abstract: Cleaning tools for cleaning the pull cable of an ingot puller apparatus and methods for cleaning the pull cable are disclosed. The cleaning tool includes a chamber for receiving the pull cable. Pressurized fluid is discharged through one or more nozzles to detach debris from the pull cable. The fluid and debris are collected in an exhaust plenum of the cleaning tool and are expelled through an exhaust tube. The cleaning tool includes one or more guides that guide the cleaning tool in an upper segment of the ingot puller apparatus.

Abstract: An electronic device includes: a back plate; an optical film disposed on the back plate; a support module disposed between the back plate and the optical film; and an adhesive layer disposed between the back plate and the support module, wherein the support module includes a base and a support unit between the base and the optical film, and the base is fixed to the back plate by the adhesive layer.

Abstract: A method of training AI for label-free cell viability determination includes a step of providing a cell sample, a step of obtaining a fluorescence image and a DHM image of the cell sample, a step of determining a first cell viability of the cell sample according to the fluorescence image of the cell sample, a step of labeling the DHM image of the cell sample as a model specifying the first cell viability, and a step of performing AI training by using the model containing the DHM image of the cell sample.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a S/D region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the S/D region, depositing an ESL on the third spacer layer, depositing an ILD layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.

Abstract: A system includes a loader tool to load a plate to which a sandpaper sheet is to be affixed to a surface of the plate. The system includes a sandpaper affixing tool to remove a liner from the sandpaper sheet to expose an adhesive surface of the sandpaper sheet, and to affix the sandpaper sheet to the surface of the plate using the adhesive surface of the sandpaper sheet. The system includes a flatness detector to determine whether a surface of the sandpaper sheet is sufficiently flat after the sandpaper sheet is affixed to the surface of the plate. The system includes an unloader tool to store the plate after the sandpaper sheet is affixed to the surface of the plate.

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.

Abstract: A thin film transistor includes a semiconductor layer, a gate, a source and a drain. The semiconductor layer includes a first heavily doped region, a second heavily doped region, a bridge region, a first channel region, a second channel region, a first lightly doped region and a second lightly doped region. The first lightly doped region connects the bridge region and the first channel region. The second lightly doped region connects the bridge region and the second channel region. The doping concentration of the bridge region is greater than that of the first lightly doped region and the second lightly doped region. The gate overlaps the bridge region, the first channel region, the second channel region, the first lightly doped region and the second lightly doped region. The source and the drain are electrically connected to the first heavily doped region and the second heavily doped region respectively.

Abstract: Provided is a bioreactor apparatus including: a liquid storage chamber for storing a liquid containing a first ion; a pump; a culture chamber for accommodating the liquid and cells to be cultured; and an ion-exchange chamber accommodating an ion-exchange substrate containing a second ion. Affinity of the second ion to the ion-exchange substrate is lower than affinity of the first ion to the ion-exchange substrate, or molar concentration of the second ion far outweigh molar concentration of the first ion. The storage chamber, the pump, the culture chamber and the ion-exchange chamber are connected via pipelines to form a closed loop, and the pump is configured to provide pressure to drive flow of the liquid in the closed loop. Also provided are a method for regulating ion concentration by the ion-exchange substrate and a method for cell culture by the bioreactor apparatus.

Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.

Abstract: An electronic device includes: a back plate; an optical film disposed on the back plate; and a support module disposed between the back plate and the optical film, wherein the support module comprises a base and a support unit between the base and the optical film, the base comprises a curved surface away from the back plate, the support unit is connected to an upper surface of the base, and the upper surface comprises the curved surface; wherein a hollow space is enclosed by the base.

Abstract: A method of reconstructing transcranial images using a dual-mode ultrasonic phased array includes steps of: controlling channels to emit energy toward an intracranial target point of a patient; respectively generating backscattered radiofrequency (RF) data by using the channels to receive backscattered energy reflected from the intracranial target; and reconstructing an acoustic distribution image based on those backscattered RF data in real-time. Compared with Pre-Treatment Ray Tracing Method, the present invention can display intracranial pressure distribution in real-time; compared with MR Thermometry, the present invention can be applied to low-energy applications without temperature change; and compared with Passive Cavitation Imaging, the present invention can stably present acoustic distribution images without relying on microbubbles.

Abstract: An active device substrate includes a substrate, a first thin film transistor located above the substrate and a second thin film transistor located above the substrate. The first thin film transistor includes a first metal oxide layer, a first gate, a first source and a first drain. A first gate dielectric layer and a second gate dielectric layer are located between the first gate and the first metal oxide layer. The second thin film transistor includes a second metal oxide layer, a second gate, a second source and a second drain. The second gate dielectric layer is located between the second gate and the second metal oxide layer, and the second metal oxide layer is located between the first gate dielectric layer and the second gate dielectric layer. The first gate and the second gate belong to a same patterned layer.

Abstract: An immersion cooling system includes a tank, an isolation plate and a condenser. The tank includes a base plate and a sidewall connected with the base plate. The sidewall defines with the base plate a space configured to accommodate a cooling liquid. The isolation plate connects with the sidewall or the base plate and divides the space into a first subsidiary space and a second subsidiary space. The first subsidiary space is configured to accommodate electronic equipment which is immersed in the cooling liquid. The isolation plate and the base plate are separated from each other. The sidewall surrounds the condenser. A vertical projection of the condenser towards the base plate at least partially overlaps with the second subsidiary space. The electronic equipment evaporates a portion of the cooling liquid to form a vapor. The condenser is configured to condense the vapor into a liquid form.

Abstract: A wireless communication device and a dynamic anti-interference method for the same are provided. The device includes at least two wireless communication circuits. When the method operates in the wireless communication device, the device monitors activities of every wireless communication circuit through a clear channel assessment method for acquiring signal strength of every wireless communication circuit. The assessment allows the device to perform a corresponding anti-interference measure for each of the wireless communication circuits. For example, when the device acknowledges that a second wireless communication circuit of the device starts to work as a first wireless communication circuit transmits or receives signals, the device controls a receiver or a transmitter of the second wireless communication circuit to perform an anti-interference measure such as a gain control for a receiver or power adjustment for a transmitter.

Abstract: An isolation estimation system includes a transmitter device, a first receiver device, a second receiver device, and a processor circuit. The transmitter device adopts a first communication technology. The transmitter device is configured to transmit a transmitting signal to the first receiving device. The second receiver device is configured to acquire a leakage signal power spectral density of a leakage signal corresponding to the transmitting signal. The second receiver device adopts a second communication technology. A bandwidth of the second communication technology is narrower than a bandwidth of the first communication technology, and the second communication technology supports a frequency hopping process. The processor circuit is configured to calculate isolation according to a signal-in-air power spectral density of the transmitting signal and the leakage signal power spectral density. The isolation is for determining whether to adjust the transmitter device.