Patents by Inventor Chih-Hung Tsai

Chih-Hung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250091100
    Abstract: Cleaning tools for cleaning the pull cable of an ingot puller apparatus and methods for cleaning the pull cable are disclosed. The cleaning tool includes a chamber for receiving the pull cable. Pressurized fluid is discharged through one or more nozzles to detach debris from the pull cable. The fluid and debris are collected in an exhaust plenum of the cleaning tool and are expelled through an exhaust tube. The cleaning tool includes one or more guides that guide the cleaning tool in an upper segment of the ingot puller apparatus.
    Type: Application
    Filed: November 8, 2024
    Publication date: March 20, 2025
    Inventors: Chin-Hung Ho, Chih-Kai Cheng, Chen-Yi Lin, Feng-Chien Tsai, Tung-Hsiao Li, YoungGil Jeong, Jin Yong Uhm
  • Publication number: 20250098237
    Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.
    Type: Application
    Filed: January 4, 2024
    Publication date: March 20, 2025
    Inventors: Jung-Hung Chang, Shih-Cheng Chen, Tsung-Han Chuang, Wen-Ting Lan, Chia-Cheng Tsai, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20250098219
    Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.
    Type: Application
    Filed: February 15, 2024
    Publication date: March 20, 2025
    Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Tsung-Han CHUANG, Fu-Cheng CHANG, Wen-Ting LAN, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG, Wang-Chun Huang, Shi-Syuan Huang
  • Publication number: 20250087533
    Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.
    Type: Application
    Filed: March 28, 2024
    Publication date: March 13, 2025
    Inventors: Ming-Hsing Tsai, Ya-Lien Lee, Chih-Han Tseng, Kuei-Wen Huang, Kuan-Hung Ho, Ming-Uei Hung, Chih-Cheng Kuo, Yi-An Lai, Wei-Ting Chen
  • Publication number: 20250077180
    Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ming-Hung Lin, Ming-En Shih, Shih-Wei Hsieh, Ping-Yuan Tsai, You-Yu Nian, Pei-Kuei Tsung, Jen-Wei Liang, Shu-Hsin Chang, En-Jui Chang, Chih-Wei Chen, Po-Hua Huang, Chung-Lun Huang
  • Publication number: 20250077282
    Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ming-Hung Lin, Ming-En Shih, Shih-Wei Hsieh, Ping-Yuan Tsai, You-Yu Nian, Pei-Kuei Tsung, Jen-Wei Liang, Shu-Hsin Chang, En-Jui Chang, Chih-Wei Chen, Po-Hua Huang, Chung-Lun Huang
  • Patent number: 12243780
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao, Jung-Hung Chang, Lo-Heng Chang, Pei-Hsun Wang, Kuo-Cheng Chiang
  • Publication number: 20250072065
    Abstract: A device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.
    Type: Application
    Filed: January 5, 2024
    Publication date: February 27, 2025
    Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Chia-Hao YU, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250071843
    Abstract: A Bluetooth connection system is provided. The Bluetooth connection system includes a control host and a Bluetooth audio device. The control host includes a transmission unit. The Bluetooth audio device wirelessly communicates with the transmission unit, wherein the control host receives an instruction, then turns on the transmission unit and executes a search task to find the Bluetooth audio device around the control host. When the Bluetooth audio device does not return a confirmation Bluetooth connection signal to the control host, the control host sends a wake-up signal to the Bluetooth audio device to start a re-pairing procedure.
    Type: Application
    Filed: July 2, 2024
    Publication date: February 27, 2025
    Applicant: BENQ CORPORATION
    Inventors: Chih-Hung LIN, Chen-Chen TSAI
  • Publication number: 20250062194
    Abstract: A semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, a first organic layer, a first inorganic layer and a first silicon-containing layer. The third conductive layer is disposed between and electrically isolated from the first conductive layer and the second conductive layer. The first organic layer continuously covers the first conductive layer and the third conductive layer. The first inorganic layer is disposed over the first organic layer. The first silicon-containing layer is inserted between the first organic layer and the first inorganic layer, wherein the second conductive layer is disposed on and disposed in the first organic layer, the first silicon-containing layer and the first inorganic layer, to electrically connect to the first conductive layer.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Patent number: 12202017
    Abstract: Cleaning tools for cleaning the pull cable of an ingot puller apparatus and methods for cleaning the pull cable are disclosed. The cleaning tool includes a chamber for receiving the pull cable. Pressurized fluid is discharged through one or more nozzles to detach debris from the pull cable. The fluid and debris are collected in an exhaust plenum of the cleaning tool and are expelled through an exhaust tube. The cleaning tool includes one or more guides that guide the cleaning tool in an upper segment of the ingot puller apparatus.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: January 21, 2025
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chin-Hung Ho, Chih-Kai Cheng, Chen-Yi Lin, Feng-Chien Tsai, Tung-Hsiao Li, YoungGil Jeong, Jin Yong Uhm
  • Publication number: 20240405167
    Abstract: A display apparatus includes a driving backplane, a first bank layer, light-emitting elements, a second bank layer, light adjusting patterns, a light-shielding pattern layer and color filter patterns. The color filter patterns includes first color filter patterns having the same color. The light-emitting elements include first light-emitting elements respectively overlapping the first color filter patterns. The light adjusting patterns include first color conversion patterns respectively overlapping the first color filter patterns. A center wavelength of one of the first light-emitting elements is greater than a center wavelength of another one of the first light-emitting elements, and a thickness of one of the first color conversion patterns is greater than a thickness of another one of the first color conversion patterns.
    Type: Application
    Filed: December 6, 2023
    Publication date: December 5, 2024
    Applicant: AUO Corporation
    Inventors: Peng-Yu Chen, Chien-Chuan Chen, Chih-Hung Tsai
  • Publication number: 20240274719
    Abstract: A thin film transistor includes a semiconductor layer, a gate, a source and a drain. The semiconductor layer includes a first heavily doped region, a second heavily doped region, a bridge region, a first channel region, a second channel region, a first lightly doped region and a second lightly doped region. The first lightly doped region connects the bridge region and the first channel region. The second lightly doped region connects the bridge region and the second channel region. The doping concentration of the bridge region is greater than that of the first lightly doped region and the second lightly doped region. The gate overlaps the bridge region, the first channel region, the second channel region, the first lightly doped region and the second lightly doped region. The source and the drain are electrically connected to the first heavily doped region and the second heavily doped region respectively.
    Type: Application
    Filed: December 7, 2023
    Publication date: August 15, 2024
    Applicant: AUO Corporation
    Inventors: Ya-Qin Huang, Yi-Da He, Chih-Hung Tsai
  • Patent number: 12041751
    Abstract: An immersion cooling system includes a tank, an isolation plate and a condenser. The tank includes a base plate and a sidewall connected with the base plate. The sidewall defines with the base plate a space configured to accommodate a cooling liquid. The isolation plate connects with the sidewall or the base plate and divides the space into a first subsidiary space and a second subsidiary space. The first subsidiary space is configured to accommodate electronic equipment which is immersed in the cooling liquid. The isolation plate and the base plate are separated from each other. The sidewall surrounds the condenser. A vertical projection of the condenser towards the base plate at least partially overlaps with the second subsidiary space. The electronic equipment evaporates a portion of the cooling liquid to form a vapor. The condenser is configured to condense the vapor into a liquid form.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: July 16, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yan-Hui Jian, Chiu-Chin Chang, Wei-Chih Lin, Ren-Chun Chang, Chih-Hung Tsai, Li-Hsiu Chen, Wen-Yin Tsai
  • Publication number: 20240156440
    Abstract: A method of reconstructing transcranial images using a dual-mode ultrasonic phased array includes steps of: controlling channels to emit energy toward an intracranial target point of a patient; respectively generating backscattered radiofrequency (RF) data by using the channels to receive backscattered energy reflected from the intracranial target; and reconstructing an acoustic distribution image based on those backscattered RF data in real-time. Compared with Pre-Treatment Ray Tracing Method, the present invention can display intracranial pressure distribution in real-time; compared with MR Thermometry, the present invention can be applied to low-energy applications without temperature change; and compared with Passive Cavitation Imaging, the present invention can stably present acoustic distribution images without relying on microbubbles.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: HAO-LI LIU, HSIANG-CHING LIN, ZHEN-YUAN LIAO, HSIANG-YANG MA, CHIH-HUNG TSAI, CHUN-HAO CHEN
  • Publication number: 20230187554
    Abstract: An active device substrate includes a substrate, a first thin film transistor located above the substrate and a second thin film transistor located above the substrate. The first thin film transistor includes a first metal oxide layer, a first gate, a first source and a first drain. A first gate dielectric layer and a second gate dielectric layer are located between the first gate and the first metal oxide layer. The second thin film transistor includes a second metal oxide layer, a second gate, a second source and a second drain. The second gate dielectric layer is located between the second gate and the second metal oxide layer, and the second metal oxide layer is located between the first gate dielectric layer and the second gate dielectric layer. The first gate and the second gate belong to a same patterned layer.
    Type: Application
    Filed: August 3, 2022
    Publication date: June 15, 2023
    Applicant: AUO Corporation
    Inventors: Chen-Shuo Huang, Shang-Lin Wu, Kuo-Kuang Chen, Chih-Hung Tsai
  • Publication number: 20230023554
    Abstract: An immersion cooling system includes a tank, an isolation plate and a condenser. The tank includes a base plate and a sidewall connected with the base plate. The sidewall defines with the base plate a space configured to accommodate a cooling liquid. The isolation plate connects with the sidewall or the base plate and divides the space into a first subsidiary space and a second subsidiary space. The first subsidiary space is configured to accommodate electronic equipment which is immersed in the cooling liquid. The isolation plate and the base plate are separated from each other. The sidewall surrounds the condenser. A vertical projection of the condenser towards the base plate at least partially overlaps with the second subsidiary space. The electronic equipment evaporates a portion of the cooling liquid to form a vapor. The condenser is configured to condense the vapor into a liquid form.
    Type: Application
    Filed: May 5, 2022
    Publication date: January 26, 2023
    Inventors: Yan-Hui JIAN, Chiu-Chin CHANG, Wei-Chih LIN, Ren-Chun CHANG, Chih-Hung TSAI, Li-Hsiu CHEN, Wen-Yin TSAI
  • Patent number: 11246102
    Abstract: A wireless communication device and a dynamic anti-interference method for the same are provided. The device includes at least two wireless communication circuits. When the method operates in the wireless communication device, the device monitors activities of every wireless communication circuit through a clear channel assessment method for acquiring signal strength of every wireless communication circuit. The assessment allows the device to perform a corresponding anti-interference measure for each of the wireless communication circuits. For example, when the device acknowledges that a second wireless communication circuit of the device starts to work as a first wireless communication circuit transmits or receives signals, the device controls a receiver or a transmitter of the second wireless communication circuit to perform an anti-interference measure such as a gain control for a receiver or power adjustment for a transmitter.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: February 8, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chien-Yu Chen, Chih-Hung Tsai
  • Patent number: 11196455
    Abstract: An isolation estimation system includes a transmitter device, a first receiver device, a second receiver device, and a processor circuit. The transmitter device adopts a first communication technology. The transmitter device is configured to transmit a transmitting signal to the first receiving device. The second receiver device is configured to acquire a leakage signal power spectral density of a leakage signal corresponding to the transmitting signal. The second receiver device adopts a second communication technology. A bandwidth of the second communication technology is narrower than a bandwidth of the first communication technology, and the second communication technology supports a frequency hopping process. The processor circuit is configured to calculate isolation according to a signal-in-air power spectral density of the transmitting signal and the leakage signal power spectral density. The isolation is for determining whether to adjust the transmitter device.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: December 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ping-Cheng Chen, Chih-Hung Tsai
  • Patent number: 10880021
    Abstract: A wireless communication device that includes an antenna module, a first communication circuit and a second communication circuit is provided. The first communication circuit performs communication by using a first communication protocol and transmits a test signal via the antenna module. The second communication circuit performs communication by using a second communication protocol and receives the test signal to calculate an isolation index based on an actual received power thereof. The second communication circuit determines that the antenna module includes two antennas when the isolation index is smaller than a threshold value to operate the first and the second communication circuits under a dual-antenna operation mode. The second communication circuit determines that the antenna module includes one antenna when the isolation index is not smaller than the threshold value to operate the first and the second communication circuits under a shared-antenna operation mode.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 29, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Pao Lin, Chih-Hung Tsai, Chih-Yuan Chou