Patents by Inventor Chih-Hung Tsai

Chih-Hung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240405167
    Abstract: A display apparatus includes a driving backplane, a first bank layer, light-emitting elements, a second bank layer, light adjusting patterns, a light-shielding pattern layer and color filter patterns. The color filter patterns includes first color filter patterns having the same color. The light-emitting elements include first light-emitting elements respectively overlapping the first color filter patterns. The light adjusting patterns include first color conversion patterns respectively overlapping the first color filter patterns. A center wavelength of one of the first light-emitting elements is greater than a center wavelength of another one of the first light-emitting elements, and a thickness of one of the first color conversion patterns is greater than a thickness of another one of the first color conversion patterns.
    Type: Application
    Filed: December 6, 2023
    Publication date: December 5, 2024
    Applicant: AUO Corporation
    Inventors: Peng-Yu Chen, Chien-Chuan Chen, Chih-Hung Tsai
  • Patent number: 12159812
    Abstract: A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: December 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Publication number: 20240391052
    Abstract: A system includes a loader tool to load a plate to which a sandpaper sheet is to be affixed to a surface of the plate. The system includes a sandpaper affixing tool to remove a liner from the sandpaper sheet to expose an adhesive surface of the sandpaper sheet, and to affix the sandpaper sheet to the surface of the plate using the adhesive surface of the sandpaper sheet. The system includes a flatness detector to determine whether a surface of the sandpaper sheet is sufficiently flat after the sandpaper sheet is affixed to the surface of the plate. The system includes an unloader tool to store the plate after the sandpaper sheet is affixed to the surface of the plate.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Yi-Fam SHIU, Cheng-Chao TSAI, Cheng-Lung WU, Chih-Hung HUANG, Jiun-Rong PAI
  • Publication number: 20240379556
    Abstract: A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Chen-Hung Tsai, Chao-Hsun Wang, Pei-Hsuan Lee, Chih-Chien Chi, Ting-Kui Chang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240377557
    Abstract: An optical element with a lanthanide compound layer in accordance with the present invention comprises: an optical substrate including a first surface; the lanthanide compound layer made of lanthanide compound and being disposed on the first surface, and the lanthanide compound layer including a second surface; and an optical film stack disposed on the second surface. With the design of the lanthanide compound layer, the optical element has a blocking effect. Therefore, during the cleaning process of the optical element, a large number of particles can be removed, while effectively suppressing the expansion and generation of pinhole defects, and maintaining the original performance of the optical element.
    Type: Application
    Filed: June 14, 2023
    Publication date: November 14, 2024
    Inventors: Sen-Tsung HSIAO, Chih-Hung CHU, Wei-Li WAN, Shi-Chun ZHOU, Chia-Sheng TSAI
  • Patent number: 12142342
    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: November 12, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Fu-Cheng Tsai, Tuo-Hung Hou, Jian-Wei Su, Yu-Hui Lin, Chih-Ming Lai
  • Publication number: 20240363464
    Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Publication number: 20240365493
    Abstract: A lifting module for a chassis and an electronic device including the lifting module are provided. The lifting module includes a sidewall bracket, a lifting bracket, a sliding button assembly, and a driven assembly. The sidewall bracket is disposed on a side frame of the chassis. The lifting bracket is movably connected to the sidewall bracket. The sliding button assembly is slidably disposed on the side frame of the chassis. Part of the sliding button assembly is exposed from the chassis. The driven assembly is movably disposed on the sidewall bracket. The driven assembly is connected to interact the sliding button assembly and the lifting bracket. The lifting bracket is driven to move relative to the sidewall bracket selectively by the sliding button assembly through the driven assembly.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 31, 2024
    Applicant: Wistron Corporation
    Inventors: Yin Tseng Lu, Chih Wei Kuo, YUCHUN HUNG, Tsung Han Yu, Hsiang Wen Huang, Chen Wei Tsai
  • Publication number: 20240355901
    Abstract: A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Chih-Hao WANG, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Zhi-Chang LIN, Chien-Ning YAO, Tsung-Han CHUANG
  • Publication number: 20240349475
    Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh SINGH, Shun-Chi TSAI, Chih-Ming LEE, Chi-Yen LIN, Kuo-Hung LO
  • Publication number: 20240335863
    Abstract: Cleaning tools for cleaning the pull cable of an ingot puller apparatus and methods for cleaning the pull cable are disclosed. The cleaning tool includes a chamber for receiving the pull cable. Pressurized fluid is discharged through one or more nozzles to detach debris from the pull cable. The fluid and debris are collected in an exhaust plenum of the cleaning tool and are expelled through an exhaust tube. The cleaning tool includes one or more guides that guide the cleaning tool in an upper segment of the ingot puller apparatus.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Inventors: Chin-Hung Ho, Chih-Kai Cheng, Chen-Yi Lin, Feng-Chien Tsai, Tung-Hsiao Li, YoungGil Jeong, Jin Yong Uhm
  • Publication number: 20240319539
    Abstract: An electronic device includes: a back plate; an optical film disposed on the back plate; a support module disposed between the back plate and the optical film; and an adhesive layer disposed between the back plate and the support module, wherein the support module includes a base and a support unit between the base and the optical film, and the base is fixed to the back plate by the adhesive layer.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 26, 2024
    Inventors: Ming-Tien WANG, Chin-Tu TSAI, Chih-Hung HSU, Chih-Hung LIU, Hsiang-Yu JUAN
  • Patent number: 12099053
    Abstract: A method of training AI for label-free cell viability determination includes a step of providing a cell sample, a step of obtaining a fluorescence image and a DHM image of the cell sample, a step of determining a first cell viability of the cell sample according to the fluorescence image of the cell sample, a step of labeling the DHM image of the cell sample as a model specifying the first cell viability, and a step of performing AI training by using the model containing the DHM image of the cell sample.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: September 24, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsiang-Chun Wei, Chih-Hsiang Liu, Chung-Lun Kuo, Chun-Wei Lo, Chia-Hung Cho, Wei-Hsiung Tsai
  • Publication number: 20240304687
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a S/D region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the S/D region, depositing an ESL on the third spacer layer, depositing an ILD layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.
    Type: Application
    Filed: August 11, 2023
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ning Yao, Chia-Hao Chang, Shih-Cheng Chen, Chih-Hao Wang, Chia-Cheng Tsai, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Tsung-Han Chuang
  • Patent number: 12083648
    Abstract: A system includes a loader tool to load a plate to which a sandpaper sheet is to be affixed to a surface of the plate. The system includes a sandpaper affixing tool to remove a liner from the sandpaper sheet to expose an adhesive surface of the sandpaper sheet, and to affix the sandpaper sheet to the surface of the plate using the adhesive surface of the sandpaper sheet. The system includes a flatness detector to determine whether a surface of the sandpaper sheet is sufficiently flat after the sandpaper sheet is affixed to the surface of the plate. The system includes an unloader tool to store the plate after the sandpaper sheet is affixed to the surface of the plate.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Fam Shiu, Cheng-Chao Tsai, Cheng-Lung Wu, Chih-Hung Huang, Jiun-Rong Pai
  • Publication number: 20240297163
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: May 12, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 12068212
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Publication number: 20240274719
    Abstract: A thin film transistor includes a semiconductor layer, a gate, a source and a drain. The semiconductor layer includes a first heavily doped region, a second heavily doped region, a bridge region, a first channel region, a second channel region, a first lightly doped region and a second lightly doped region. The first lightly doped region connects the bridge region and the first channel region. The second lightly doped region connects the bridge region and the second channel region. The doping concentration of the bridge region is greater than that of the first lightly doped region and the second lightly doped region. The gate overlaps the bridge region, the first channel region, the second channel region, the first lightly doped region and the second lightly doped region. The source and the drain are electrically connected to the first heavily doped region and the second heavily doped region respectively.
    Type: Application
    Filed: December 7, 2023
    Publication date: August 15, 2024
    Applicant: AUO Corporation
    Inventors: Ya-Qin Huang, Yi-Da He, Chih-Hung Tsai
  • Publication number: 20240263122
    Abstract: Provided is a bioreactor apparatus including: a liquid storage chamber for storing a liquid containing a first ion; a pump; a culture chamber for accommodating the liquid and cells to be cultured; and an ion-exchange chamber accommodating an ion-exchange substrate containing a second ion. Affinity of the second ion to the ion-exchange substrate is lower than affinity of the first ion to the ion-exchange substrate, or molar concentration of the second ion far outweigh molar concentration of the first ion. The storage chamber, the pump, the culture chamber and the ion-exchange chamber are connected via pipelines to form a closed loop, and the pump is configured to provide pressure to drive flow of the liquid in the closed loop. Also provided are a method for regulating ion concentration by the ion-exchange substrate and a method for cell culture by the bioreactor apparatus.
    Type: Application
    Filed: September 14, 2023
    Publication date: August 8, 2024
    Inventors: Ching-Yun Chen, Chih-Hung Wang, Hsin-Chien Chen, Yu-Hsuan Ting, Chun-Yi Peng, Yueh-Teng Tsai, Sheng-Wen Chang, Feng-Yuan Chien
  • Patent number: 12052851
    Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Shun-Chi Tsai, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo