Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.

Abstract: Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device may include a photodiode device electrically connected to a metal-insulator-metal deep-trench capacitor. The metal-insulator-metal deep-trench capacitor includes a layer of an amorphous material between an insulator layer stack of the deep-trench capacitor structure and a capacitor bottom metal layer of the metal-insulator-metal deep-trench capacitor. The amorphous material includes a bandgap energy level that provides a conduction band offset and lowers a probability of electron tunneling from the capacitor bottom metal electrode layer to the insulator layer stack. In this way, leakage associated with grain boundaries, crystal defects, and interfaces of a bottom layer of the insulator layer stack may be overcome to improve a lag performance of the semiconductor device including the metal-insulator-metal deep-trench capacitor.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.

Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Abstract: An integrated chip including a semiconductor substrate. The semiconductor substrate includes a first region having a first doping type, a second region having a second doping type, different than the first doping type, and a third region having the second doping type. A photodetector is in the semiconductor substrate. The photodetector is formed, at least in part, by the first region and the second region. A first capacitor electrode is over the third region of the semiconductor substrate. The first capacitor electrode includes a semiconductor. A first insulator layer is between the first capacitor electrode and the third region. A capacitor is along the semiconductor substrate. The capacitor is formed, at least in part, by the first capacitor electrode, the third region, and the first insulator layer.

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Abstract: A nano-twinned Cu—Ni alloy layer is provided, wherein more than 50% in volume of the nano-twinned Cu—Ni alloy layer comprises plural twinned grains, the plural twinned grains comprise plural columnar twinned grains, and a Ni content in the nano-twinned Cu—Ni alloy layer is in a range from 0.05 at % to 20 at %. In addition, a method for manufacturing the aforesaid nano-twinned Cu—Ni alloy layer is also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.

Abstract: A display device includes: a display panel including a first substrate with a first surface and a second substrate disposed on the first surface; a third substrate, wherein the second substrate is disposed between the first substrate and the third substrate, and the third substrate has a second surface facing the first surface; an adhesion element disposed on the first surface and adjacent to the second substrate, wherein the adhesion element has a first through hole; and a filler disposed in the first through hole and in contact with the first surface and the second surface. The first through hole of the adhesion element has an area defined as a first area, the filler has a region in contact with the second surface, and an area of the region is defined as a second area. The ratio of the first area to the second area ranges from 0.5 to 0.99.

Abstract: A display device includes: a display panel including a first substrate with a first surface and a second substrate disposed on the first surface; a third substrate, wherein the second substrate is disposed between the first substrate and the third substrate, and the third substrate has a second surface facing the first surface; an adhesion element disposed on the first surface and adjacent to the second substrate, wherein the adhesion element has a first through hole; and a filler disposed in the first through hole and in contact with the first surface and the second surface. The first through hole of the adhesion element has an area defined as a first area, the filler has a region in contact with the second surface, and an area of the region is defined as a second area. The ratio of the first area to the second area ranges from 0.5 to 0.99.

Abstract: A memory heat sink device having an enlarged heat dissipating area is provided. The memory heat sink device includes two cooling fins that are respectively attached to a front side and a back side of a memory. Raised dots are protruded from a front (or back) side of the cooling fin attached to the front (or back) side of the memory. Each of the raised dots on the cooling fin has at least one sectional area and at least one connection portion. Thus, the heat sink area of the cooling fin increases and heat generated by the memory is easily dissipated by the sectional area through thermal convection.

Abstract: A memory heat sink device provided with an extra heat sink area includes two cooling fins that are respectively attached to the front and back sides of a memory. A plurality of raised dots that protrude toward the front side are formed on the cooling fin attached to the front side of the memory. Each of the raised dots and the cooling fin has at least one sectional area and one connection portion. Thus, the heat sink area of cooling fin increases and the sectional area is used to easily dissipate heat generated by the memory in the manner of convection.