Patents by Inventor Chih-I Lin

Chih-I Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200080942
    Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).
    Type: Application
    Filed: March 16, 2018
    Publication date: March 12, 2020
    Applicant: iXensor CO., LTD.
    Inventors: Yenyu CHEN, An Cheng CHANG, Tai I CHEN, Su Tung YANG, Chih Jung HSU, Chun Cheng LIN, Min Han WANG, Shih Hao CHIU
  • Publication number: 20200078414
    Abstract: The present invention provides a method of preventing or treating obesity by administering the probiotic bacterium of a novel Parabacteroides goldsteinii strain to the subject in need. The novel Parabacteroides goldsteinii strain is derived from the gastrointestinal tract of an individual and has better aero-tolerance and better acid-tolerance therefore it has better environmental tolerance to adapt to different living environments. The novel Parabacteroides goldsteinii strain not only can effectively prevent the weight gain of the individual, but also can effectively slow down the weight gain of the obese individual; therefore, the novel Parabacteroides goldsteinii strain of the present invention can be used for preparing a pharmaceutical composition for prevention and/or treating obesity.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 12, 2020
    Inventors: Po-I Wu, Chih-Jung Chang, Yu-Ling Tsai, Tzu-Lung Lin
  • Patent number: 10545924
    Abstract: Embodiments relate to a system, method and program product for performing code conversions. In one embodiment the method includes determining size of encoding space for a source file and a target file upon receipt of a code conversion request and generating a main conversion file upon determination that a target encoding space associated with said target file is smaller than a source encoding space associated with the source file. Subsequently an extension converted file is generated from the source file according to a pre-established mapping table of code conversion stored in a memory. The code conversion request is completed by using the main conversion file and said extension file together so that the source file does not need to be truncated in order to fit into the target conversion space.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Albert Hsieh, Elaine I H. Liao, Chih-Yuan Lin, Pei-Yi Lin
  • Patent number: 10533252
    Abstract: A showerhead is configured to be mounted inside a processing chamber and provide a processing gas onto a semiconductor wafer inside the processing chamber. The showerhead includes a supply plenum, a faceplate, and an electrode plate assembly. The faceplate is disposed at a side of the supply plenum. The electrode plate assembly is disposed between a gas source and the supply plenum. The electrode plate assembly includes a first plate having a unitary construction and having a plurality of first gas holes, and a second plate having a unitary construction and having a plurality of second gas holes. The second plate is located between the first plate and the supply plenum and separated from the first plate. The plurality of second gas holes are partially overlapped but misaligned with the plurality of first gas holes. A semiconductor apparatus having the same and a semiconductor process are also provided.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Chiu, Ding-I Liu, Chin-Feng Lin, Po-Hsiung Leu
  • Patent number: 10529825
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20200004137
    Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 2, 2020
    Inventors: Ru-Gun LIU, Chin-Hsiang LIN, Cheng-I HUANG, Chih-Ming LAI, Lai Chien WEN, Ken-Hsien HSIEH, Shih-Ming CHANG, Yuan-Te HOU
  • Publication number: 20190388230
    Abstract: An artificial joint includes a first joint assembly and a second joint assembly. The first joint assembly is adapted to be connected to a first bone and has a first contacting surface, wherein the first contacting surface includes a first convex arc surface, a second convex arc surface, and a third convex arc surface. The second joint assembly is adapted to be connected to a second bone and has a second contacting surface, wherein the second contacting surface is in contact with the first contacting surface and includes a first concave arc surface, a second concave arc surface, and a third concave arc surface, and the first concave arc surface, the second concave arc surface, and the third concave arc surface respectively correspond to the first convex arc surface, the second convex arc surface, and the third convex arc surface.
    Type: Application
    Filed: December 19, 2018
    Publication date: December 26, 2019
    Applicants: Industrial Technology Research Institute, National Taiwan University Hospital
    Inventors: Pei-I Tsai, Hsin-Hsin Shen, Kuo-Yi Yang, De-Yau Lin, Yi-Hung Wen, Chih-Chieh Huang, Wei-Luan Fan, Pei-Yu Chen, Ching-Chi Hsu
  • Patent number: 10504834
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20190296124
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.
    Type: Application
    Filed: April 11, 2018
    Publication date: September 26, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20190273042
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 10395991
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10385443
    Abstract: A device for growing large-sized monocrystalline crystals, including a crucible adapted to grow crystals from a material source and with a seed crystal and including therein a seed crystal region, a growth chamber, and a material source region; a thermally insulating material disposed outside the crucible and below a heat dissipation component; and a plurality of heating components disposed outside the thermally insulating material to provide heat sources, wherein the heat dissipation component is of a heat dissipation inner diameter and a heat dissipation height which exceeds a thickness of the thermally insulating material.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: August 20, 2019
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Dai-Liang Ma, Hsueh-I Chen, Bo-Cheng Lin, Cheng-Jung Ko, Ying-Cong Zhao, Chih-Wei Kuo, Shu-Yu Yeh
  • Patent number: 10388518
    Abstract: An epitaxial substrate and a method of manufacturing the same are provided. The epitaxial substrate includes a handle substrate, a heat dissipation layer on the handle substrate, a high-resistance silicon substrate on the heat dissipation layer, and a III-V semiconductor layer grown on the high-resistance silicon substrate. The heat dissipation layer has high thermal conductivity. The high-resistance silicon substrate has a resistance more than 100 ohm·cm. Diameters of the high-resistance silicon substrate and the III-V semiconductor film are smaller than a diameter of the handle substrate, such that the epitaxial substrate is a convex substrate.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 20, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chun-I Fan, Chih-Yuan Chuang, Man-Hsuan Lin, Wen-Ching Hsu
  • Publication number: 20190221469
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 18, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10347526
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate structure, and a conductive element. The gate structure is on the substrate. The gate structure includes a gate electrode and a cap layer on the gate electrode. The conductive element is adjoined with an outer surface of the gate structure. The conductive element includes a lower conductive portion and an upper conductive portion electrically connected on the lower conductive portion and adjoined with the cap layer. The lower conductive portion and the upper conductive portion have an interface therebetween. The interface is below an upper surface of the cap layer.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20190201061
    Abstract: An expandable orthopedic implant includes a casing pipe, a shaft, a first expandable element and a first link lever. The casing pipe has a first opening, a second opening and an axis passing through the first and second opening. The casing pipe sheathes one end of the shaft, and the other end of the shaft has a top portion disposed out of the first opening. The first expandable element has a first terminal pivoted on the casing pipe and a second terminal. The first link lever has a proximal end pivoted to the top portion and a distal end pivoted to the second terminal. When the top portion is driven moving away from the first opening along an extending direction of the axis, the first link-lever can be pushed by the shaft to enact the second terminal moving away from the axis along a direction perpendicular to the axis.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, National Taiwan University Hospital
    Inventors: Pei-I TSAI, Hsin-Hsin SHEN, Kuo-Yi YANG, Shih-Ping LIN, Jui-Sheng SUN, Chih-Yu CHEN, Yu-Tsung CHIU, Chun-Ti CHEN, De-Yau LIN, An-Li CHEN
  • Publication number: 20190206672
    Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.
    Type: Application
    Filed: February 11, 2019
    Publication date: July 4, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20190172752
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20190157423
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 23, 2019
    Inventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
  • Publication number: 20170196799
    Abstract: A skincare stimulant having an effective dose of platelets and pharmaceutically acceptable solvents and/or excipients, wherein the effective dose refers to the presence of at least 1000 platelets in every milligram of skincare stimulant.
    Type: Application
    Filed: January 13, 2017
    Publication date: July 13, 2017
    Applicant: CENTRAL MEDICAL TECHNOLOGIES INC.
    Inventors: Chih I LIN, Han-Lei WAN