Patents by Inventor Chih-I Wu
Chih-I Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145421Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.Type: ApplicationFiled: October 27, 2023Publication date: May 2, 2024Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
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Patent number: 11967272Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.Type: GrantFiled: December 9, 2022Date of Patent: April 23, 2024Assignees: AUO Corporation, National Cheng-Kung UniversityInventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
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Patent number: 11949001Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.Type: GrantFiled: March 21, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Ching Wang, Chung-I Yang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
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Publication number: 20240096388Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chao-I WU, Chih-Yu CHANG, Yu-Ming LIN
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Publication number: 20240014035Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, a source/drain structure, a contact, a dielectric layer, and a metal line. The gate structure is on the semiconductor substrate. The source/drain structure is adjacent to the gate structure. The contact lands on the source/drain structure. The dielectric layer spas the contact and the gate structure. The metal line extends through the dielectric layer to the contact. The metal line includes a liner over the contact, a magnetic layer over the liner, a graphene layer over the magnetic layer, and a filling metal over the graphene layer. The magnetic layer has a greater permeability coefficient than the filling metal.Type: ApplicationFiled: September 21, 2023Publication date: January 11, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jian-Zhi HUANG, Yun-Hsuan HSU, I-Chih NI, Chih-I WU
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Patent number: 11855150Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.Type: GrantFiled: May 27, 2022Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Yun-Yuan Wang, Chih-Hsiang Hsiao, I-Chih Ni, Chih-I Wu
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Publication number: 20230317852Abstract: A method includes forming a 2-D semiconductor material layer over a substrate; forming source/drain contacts over source/drain regions of the 2-D semiconductor material layer; and forming a gate structure over a channel region of the 2-D semiconductor material layer. Forming the source/drain contacts includes performing a first deposition process to deposit a first metal layer over the 2-D semiconductor material layer; and after the first deposition process is completed, performing a second deposition process to deposit a second metal layer over the first metal layer, in which the second metal layer has a higher melting point than the first metal layer.Type: ApplicationFiled: March 18, 2022Publication date: October 5, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Shun-Siang JHAN, Ang-Sheng CHOU, I-Chih NI, Chih-I WU
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Publication number: 20230276720Abstract: A method includes forming a transistor over a substrate; and forming a resistive element over the transistor, in which forming the resistive element includes forming a bottom electrode electrically connected to a source/drain region of the transistor; forming a resistive switching layer over the bottom electrode, in which the resistive switching layer is made of metal halide; and forming a top electrode over the resistive switching layer.Type: ApplicationFiled: February 25, 2022Publication date: August 31, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chia-Shuo LI, Yu-Tien WU, Bo-You CHEN, I-Chih NI, Chih-I WU
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Publication number: 20230009266Abstract: A method for forming an integrated circuit device is provided. The method includes forming a transistor over a frontside of a substrate; forming an interconnect structure over the transistor; depositing a first transition metal layer over the interconnect structure; performing a plasma treatment to turn the first transition metal layer into a first transition metal dichalcogenide layer; forming a dielectric layer over the first transition metal dichalcogenide layer; forming a first gate electrode over the dielectric layer and a first portion of the first transition metal dichalcogenide layer; and forming a first source contact and a first drain contact respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer, the first portion of the first transition metal dichalcogenide layer being between the second and third portions of the first transition metal dichalcogenide layers.Type: ApplicationFiled: January 25, 2022Publication date: January 12, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Ting CHANG, Jian-Zhi HUANG, Jin-Bin YANG, I-Chih NI, Chih-I WU
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Patent number: 11491648Abstract: A linear motion actuation system and method of using the same may be utilized for installing or removing a server blade within a server rack, via a linear motion assembly fastened to a server blade and configured for linear motion with the server blade; a bracket fastened to a server rack; and at least one linear motion actuator comprising: a first component secured with the linear motion assembly; and a second component movably secured with the first component and secured with the bracket. The second component is configured for at least substantially linear movement relative to first component, and the at least one linear motion actuator is configured to, upon receipt of a signal from a controller, move the second component in an at least substantially linear direction relative to the first component to move the server blade relative to the server rack.Type: GrantFiled: January 14, 2020Date of Patent: November 8, 2022Assignee: Synopsys, Inc.Inventor: Chih I. Wu
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Publication number: 20220293735Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.Type: ApplicationFiled: May 27, 2022Publication date: September 15, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Yun-Yuan WANG, Chih-Hsiang HSIAO, I-Chih NI, Chih-I WU
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Patent number: 11406022Abstract: A method of fabricating a substrate having a through via includes: providing a carrier board having a release layer thereon; attaching the substrate onto the carrier board via the release layer; applying a light beam to the substrate to form a first blind hole in the substrate, wherein the first blind hole penetrates a first surface and a second surface of the substrate; performing an enlargement process on the first blind hole to form a second blind hole; forming a through via in the second blind hole; and performing a de-bonding process to release the substrate having a through via from the carrier board.Type: GrantFiled: December 24, 2020Date of Patent: August 2, 2022Assignee: Industrial Technology Research InstituteInventors: Chih-I Wu, Shih-Ming Lin, Pin-Hao Hu, Yu-Chung Lin, Hsin-Yu Chang, Fu-Lung Chou, Chien-Jung Huang
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Publication number: 20220238332Abstract: A plasma enhanced chemical vapor deposition (PECVD) method includes loading a wafer having a magnetic layer thereon into a processing chamber equipped with a radio frequency (RF) system, introducing an aromatic hydrocarbon precursor into the processing chamber, and turning on an RF source of the RF system to decompose the aromatic hydrocarbon precursor into active radicals at a frequency greater than about 1000 Hz to form a graphene layer over the magnetic layer.Type: ApplicationFiled: May 6, 2021Publication date: July 28, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jian-Zhi HUANG, Yun-Hsuan HSU, I-Chih NI, Chih-I WU
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Patent number: 11362180Abstract: A semiconductor device includes a substrate, a channel stack, source/drain contacts, and a gate electrode. The channel stack is over the substrate and includes a 2D channel layer and a barrier layer. An energy band gap of the barrier layer is greater than an energy band gap of the 2D channel layer. The source/drain contacts are in contact with the channel stack. The gate electrode is above the substrate.Type: GrantFiled: December 19, 2019Date of Patent: June 14, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Yun-Yuan Wang, Chih-Hsiang Hsiao, I-Chih Ni, Chih-I Wu
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Publication number: 20220141961Abstract: A method of fabricating a substrate having a through via includes: providing a carrier board having a release layer thereon; attaching the substrate onto the carrier board via the release layer; applying a light beam to the substrate to form a first blind hole in the substrate, wherein the first blind hole penetrates a first surface and a second surface of the substrate; performing an enlargement process on the first blind hole to form a second blind hole; forming a through via in the second blind hole; and performing a de-bonding process to release the substrate having a through via from the carrier board.Type: ApplicationFiled: December 24, 2020Publication date: May 5, 2022Applicant: Industrial Technology Research InstituteInventors: Chih-I Wu, Shih-Ming Lin, Pin-Hao Hu, Yu-Chung Lin, Hsin-Yu Chang, Fu-Lung Chou, Chien-Jung Huang
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Patent number: 11232982Abstract: A method includes loading a wafer into a processing chamber, wherein the processing chamber is wound by a coil, and the coil is coupled to an RF system; supplying an aromatic hydrocarbon precursor into the processing chamber; after supplying the aromatic hydrocarbon precursor, turning on an RF power of the RF system to decompose the aromatic hydrocarbon precursor into active radicals and cyclize the active radicals into a graphene layer over a metal layer on the wafer; and after an entirety of the metal layer being covered by the graphene layer, turning off the RF power of the RF system to stop forming the graphene layer.Type: GrantFiled: January 10, 2020Date of Patent: January 25, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jian-Zhi Huang, Yun-Hsuan Hsu, I-Chih Ni, Chih-I Wu
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Patent number: 11171460Abstract: A tool for coupling and decoupling a connector of a cable. The tool includes a body, a bracket, and a first hook. The body has a first end portion, a second end portion opposite the first end portion, and an intermediate portion between the first end portion and the second end portion. The body has a longitudinal axis running between the first end portion and second end portion. The body also has a first surface and a second surface opposite the first surface. The bracket is disposed at the first end portion. The bracket defines a cavity configured to receive a portion of the connector, and the bracket is configured to push the connector as the tool moves in a first direction. The first hook is disposed at the intermediate portion. The first hook is configured to engage an opening defined by the connector and pull the connector as the tool moves in a second direction different than the first direction.Type: GrantFiled: February 20, 2020Date of Patent: November 9, 2021Assignee: Synopsys, Inc.Inventor: Chih I Wu
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Publication number: 20210217660Abstract: A method includes loading a wafer into a processing chamber, wherein the processing chamber is wound by a coil, and the coil is coupled to an RF system; supplying an aromatic hydrocarbon precursor into the processing chamber; after supplying the aromatic hydrocarbon precursor, turning on an RF power of the RF system to decompose the aromatic hydrocarbon precursor into active radicals and cyclize the active radicals into a graphene layer over a metal layer on the wafer; and after an entirety of the metal layer being covered by the graphene layer, turning off the RF power of the RF system to stop forming the graphene layer.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jian-Zhi HUANG, Yun-Hsuan HSU, I-Chih NI, Chih-I WU
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Publication number: 20210193801Abstract: A semiconductor device includes a substrate, a channel stack, source/drain contacts, and a gate electrode. The channel stack is over the substrate and includes a 2D channel layer and a barrier layer. An energy band gap of the barrier layer is greater than an energy band gap of the 2D channel layer. The source/drain contacts are in contact with the channel stack. The gate electrode is above the substrate.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Yun-Yuan WANG, Chih-Hsiang HSIAO, I-Chih NI, Chih-I WU
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Publication number: 20200223060Abstract: A linear motion actuation system and method of using the same may be utilized for installing or removing a server blade within a server rack, via a linear motion assembly fastened to a server blade and configured for linear motion with the server blade; a bracket fastened to a server rack; and at least one linear motion actuator comprising: a first component secured with the linear motion assembly; and a second component movably secured with the first component and secured with the bracket.Type: ApplicationFiled: January 14, 2020Publication date: July 16, 2020Inventor: Chih I. Wu