Abstract: A hybrid cluster system includes at least one computing node for providing computing resources and at least one storage node for providing storage resources. A specification of the at least one computing node is identical to a specification of the at least one storage node.

Abstract: A server switch system includes a switch unit and a field-programmable gate array (FPGA) unit. The switch unit includes a first switch interface for receiving the first data and sending the second data, and a second switch interface for sending the third data and receiving the fourth data. The switch unit is used to generate the third data according to the first data, and generate the second data according to the fourth data. The FPGA unit includes an FPGA interface coupled to the second switch interface for receiving the third data from the switch unit and sending the fourth data to the switch unit.

Abstract: A test apparatus for a server includes a first connection unit coupled to a mother board of the server, a second connection unit coupled to a device under test, a data transmission unit, a processing unit, and a network unit. According to a selection signal, the data transmission unit switches one of data transmission modes to perform data transmission between the first connection unit and the second connection unit. The processing unit controls the data transmission unit to perform a first test program for the mother board through the first connection unit, or perform a second test program for the device under test through the first connection unit and the second connection unit. The network unit receives a control signal generated by an external apparatus, so that the external apparatus controls the processing unit to perform the first test program and the second test program through the network unit.

Abstract: A test apparatus for a server includes a first connection unit coupled to a mother board of the server, a second connection unit coupled to a device under test, a data transmission unit, a processing unit, and a network unit. According to a selection signal, the data transmission unit switches one of data transmission modes to perform data transmission between the first connection unit and the second connection unit. The processing unit controls the data transmission unit to perform a first test program for the mother board through the first connection unit, or perform a second test program for the device under test through the first connection unit and the second connection unit. The network unit receives a control signal generated by an external apparatus, so that the external apparatus controls the processing unit to perform the first test program and the second test program through the network unit.

Abstract: A testing device comprising a power unit, a storage unit, and a controlling unit is mentioned. The power unit is adapted to provide different voltages. The storage unit is adapted to store a power sequence table and a simulation signal generating table. The controlling unit couples with the power unit and the storage unit, wherein the controlling unit is adapted to provide power sequence controlling signals according to the power sequence table, and the power unit is adapted to provide the voltages to the unit under test according to the power sequence controlling signals. The controlling unit is adapted to provide a simulation signal to the unit under test according to the simulation signal generating table, and the controlling unit is adapted to receive state signals generated by the unit under test in response to the voltages and the simulation signal.

Abstract: A system and method for monitoring an input/output port status of peripheral devices are used for monitoring an operating status of each peripheral device of a main board. The system includes at least one peripheral device, a complex programmable logic device (CPLD), and an output apparatus. The CPLD is electrically connected to the peripheral devices. The CPLD further includes a protocol conversion unit and multiple data registers. The protocol conversion unit converts an operating status of the CPLD or the peripheral devices into device status information. The data register is used for storing the device status information. The output apparatus is electrically connected to the CPLD. The output apparatus is used for displaying the device status information in the data register. A user can observe the operating status of each of the peripheral devices of the main board conveniently.

Abstract: A method for detecting a capacitor loss is applicable to detecting a plurality of by-pass capacitors connected in parallel to each other. The detection method includes the following steps, an alternating current (AC) signal is input into the by-pass capacitors, in which the AC signal has a plurality of test frequencies; test voltages of the by-pass capacitors at each of the test frequencies are recorded, so as to form a test result table; it is determined whether the test result table is the same as a standard voltage table; and when a result of the determination is NO, a fail signal is output. By applying the detection method, whether a loss exists in the by-pass capacitors can be effectively identified, thereby solving the problem that small capacitors are undetectable when large capacitors are connected in parallel to the small capacitors.

Abstract: A monitoring system and method of the power sequence signals are presented, so as to monitor a power sequence signals transmitted via the peripheral devices of a motherboard in operation process. The monitoring system includes a power supply unit and a Complex Programmable Logic Device (CPLD). The monitoring method includes activating the motherboard, and driving the CPLD to select any one of the peripheral devices in sequence being electrified; controlling, by the CPLD, operation powers of the peripheral devices through a General Purpose Input/Output (GPIO) pin, and recording the power sequence signals of the peripheral devices under different operation powers in a data register; and outputting, by the CPLD, the power sequence signals of the peripheral devices.

Abstract: A processing system for monitoring the power-on self-test information is used for monitoring an operating state of a complex programmable logic device (CPLD) of a main board. The processing system includes a basic input/output system (BIOS) device, a CPLD and a monitoring device. The BIOS device sends power-on self-test information at a first frequency. The CPLD is electrically connected to the BIOS device. The CPLD further includes a first in first out (FIFO) register, and the FIFO register is used for storing the received power-on self-test information. The CPLD sends the power-on self-test information stored in the FIFO register at a second frequency. The monitoring device is electrically connected to the CPLD. The monitoring device is used for receiving the power-on self-test information sent from the CPLD.

Abstract: A testing method for a unit under test is provided. At least one unit under test is electrically connected to a testing machine. The testing machine creates a test script and executes the test script, so as to perform a non-operating system (OS) test and an OS test on the unit under test, and the testing machine is capable of combining the testing results, so a testing process is simplified, a test time is shortened, and test accuracy is improved.

Abstract: A multi-chip test system and a method thereof utilize a Complex Programmable Logic Device (CPLD) to be connected in series to multiple chips having a Joint Test Action Group (JTAG) interface for function inspection. The test system includes a device to-be-tested and a control device. The device to-be-tested includes multiple chips, a CPLD, and a second JTAG interface. Each of the chips has a first JTAG interface. The CPLD is coupled to the chips through the first JTAG interfaces. The second JTAG interface is connected to the CPLD. The control device is connected to the second JTAG interface and used for sending a switching instruction to the CPLD. In the test method, firstly, a switching instruction is received to select a chip to-be-tested; then, a test signal is sent to the chip to-be-tested according to the chip to-be-tested; and the chip to-be-tested transfers a test result back to a CPLD according to the test signal.

Abstract: A motherboard error detection system includes a pluggable error detection board and a motherboard having a boot management chip. When the motherboard enters a device-driven status from a standby status, the boot management chip is used to manage power-on timings of different voltage sources; to collect a plurality of sets of status information; and to check whether the sets of status information and the power-on timings have errors. The pluggable error detection board includes an interpreting unit, a message-reading interface and a connector which is pluggably disposed on the motherboard. When the boot management chip notifies the pluggable error detection board to read an error message, the interpreting unit converts the error message to human-readable information, and the human-readable information is outputted through the message-reading interface.

Abstract: A test board is provided. The test board includes a power connecting interface, diode modules, a power module a detecting module, and a processor. The power connecting interface includes power pins, wherein each of the power pins is electrically connected to a motherboard power socket to receive a power signal. Each of the diode modules is electrically connected to one of the power pins and includes at least one diode. The power module is electrically connected to the diode modules to receive the power signal through each of the diode modules. The detection module is electrically connected to points between the diode modules and the power connecting interface to generate a detection result according to the voltage between each diode module and the power connecting interface. The processor is used to determine the connecting state between the power pin and the corresponding motherboard power socket according to the detection result.

Abstract: A motherboard error detection system includes a pluggable error detection board and a motherboard having a boot management chip. When the motherboard enters a device-driven status from a standby status, the boot management chip is used to manage power-on timings of different voltage sources; to collect a plurality of sets of status information; and to check whether the sets of status information and the power-on timings have errors. The pluggable error detection board includes an interpreting unit, a message-reading interface and a connector which is pluggably disposed on the motherboard. When the boot management chip notifies the pluggable error detection board to read an error message, the interpreting unit converts the error message to human-readable information, and the human-readable information is outputted through the message-reading interface.

Abstract: A test board is provided. The test board includes a power connecting interface, diode modules, a power module a detecting module, and a processor. The power connecting interface includes power pins, wherein each of the power pins is electrically connected to a motherboard power socket to receive a power signal. Each of the diode modules is electrically connected to one of the power pins and includes at least one diode. The power module is electrically connected to the diode modules to receive the power signal through each of the diode modules. The detection module is electrically connected to points between the diode modules and the power connecting interface to generate a detection result according to the voltage between each diode module and the power connecting interface. The processor is used to determine the connecting state between the power pin and the corresponding motherboard power socket according to the detection result.

Abstract: A recording method for writing data into an electrically erasable programmable read-only memory is disclosed, in which the memory has already been electrically connected to a controller through a logic device. The method sets the logic devices for the first time to disconnect the memory from the controller, and set the logic devices for the second time to write setting data required by the controller into the memory. After that, the method reads out the setting data stored in the memory to confirm the writing of the setting data, and connects the memory to the controller again.

Abstract: The present invention discloses a machine for programming on-board chipsets, wherein the on-board chipsets means that some chipsets are mounted on a circuit board, and the circuit board has a plurality of input pads electrically connected to each chipset individually. The machine comprises a platform, a number of programming modules and an IC programming burner in which the platform faces a surface of the circuit board having the input pads, the programming modules disposed movably on the platform separately extends a number of output pins outwardly so that for connecting electrically an input pad as contacting the input pad, and the IC programming burner electrically connected to each of the programming modules separately distributes a set of programming codes into each programming module when the output pins electrically connect to the input pads.