Patents by Inventor Chih Jen Hsu
Chih Jen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150236682Abstract: A clock adjustment circuit and a digital to analog converting device are provided. The clock adjustment circuit includes a selection circuit and a frequency decreasing circuit. The selection circuit is configured to generate a first selection signal in response to a frequency of an output clock signal. The frequency decreasing circuit is coupled to the selection circuit, and configured to generate the output clock signal by reducing a frequency of an input clock signal by a first ratio in response to a first level of the first selection signal, and configured to generate the output clock signal by reducing the frequency of the input clock signal by a second ratio in response to a second level of the first selection signal, wherein the first ratio is different from the second ratio. Accordingly, complexity of a circuit is reduced.Type: ApplicationFiled: May 13, 2014Publication date: August 20, 2015Applicant: Phisontech Electronics (Malaysia) Sdn Bhd.Inventors: Nyuk-How Thian, Chih-Jen Hsu
-
Publication number: 20150009615Abstract: A pad structure for disposing an electronic component on a printed circuit board is provided. The pad structure includes a first pad and a plurality of second pads. The first pad is configured to couple to a terminal of the electronic component. Each of the second pads is configured to couple to another terminal of the electronic component. The first pad and the second pads are electrically independent to each other, and the second pads are electrically independent to each other. Besides, a printed circuit board and a memory storage device using the pad structure are also provided.Type: ApplicationFiled: October 18, 2013Publication date: January 8, 2015Applicant: Phison Electronics Corp.Inventors: Chih-Jen Hsu, Chun-Feng Lee
-
Patent number: 8706952Abstract: A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks.Type: GrantFiled: April 23, 2010Date of Patent: April 22, 2014Assignee: Phison Electronics Corp.Inventors: Chih-Jen Hsu, Yi-Hsiang Huang, Chung-Lin Wu
-
Patent number: 8219883Abstract: Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.Type: GrantFiled: June 30, 2008Date of Patent: July 10, 2012Assignee: Phison Electronics Corp.Inventors: Chih-Jen Hsu, Yi-Hsiang Huang
-
Patent number: 8046645Abstract: A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged.Type: GrantFiled: June 16, 2008Date of Patent: October 25, 2011Assignee: Phison Electronics Corp.Inventors: Chih-Jen Hsu, Yi-Hsiang Huang
-
Publication number: 20110191525Abstract: A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks.Type: ApplicationFiled: April 23, 2010Publication date: August 4, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Jen Hsu, Yi-Hsiang Huang, Chung-Lin Wu
-
Patent number: 7949929Abstract: A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the controller both writes all 0xFF data in the data area and writes all 0xFF error-correcting codes in the error-correcting code area, the first inverting circuit inverts the all 0xFF data and the all 0xFF error-correcting codes into all 0x00 data and all 0x00 error-correcting codes, respectively.Type: GrantFiled: June 5, 2007Date of Patent: May 24, 2011Assignee: Phison Electronics Corp.Inventors: Ming-Jen Liang, Wee-Kuan Gan, Chih-Jen Hsu
-
Publication number: 20090259916Abstract: Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.Type: ApplicationFiled: June 30, 2008Publication date: October 15, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Jen Hsu, Yi-Hsiang Huang
-
Publication number: 20090259896Abstract: A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged.Type: ApplicationFiled: June 16, 2008Publication date: October 15, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Jen Hsu, Yi-Hsiang Huang
-
Publication number: 20090182932Abstract: A method for managing blocks is provided. In the method, a plurality of flash memories is divided into a plurality of block program units, and blocks mapped to each of the block program units are recorded, wherein each of the block program units maps to at least two blocks. Next, available states of the block program units are respectively determined according to good or bad states of the mapped blocks. Final, good blocks within the block program units are recorded, so as to provide the good blocks within the block program units according to the record for being written with data. Accordingly, it is possible to fully utilize the blocks in the flash memories.Type: ApplicationFiled: March 24, 2008Publication date: July 16, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Wee-Tah Tan, Jiunn-Yeong Yang, Chih-Jen Hsu, Wee-Kuan Gan
-
Patent number: 7319360Abstract: The present invention describes a modulator including a differential amplifier connected to a reference voltage and a first transistor, and the first transistor is connected to a feedback device, and a second transistor is set between the first transistor and the differential amplifier and connected to a voltage detector and a diode, and the diode is connected to a power supply, and the voltage detector keeps on detecting an output voltage (VOUT) between the feedback device and the first transistor. If the output voltage (VOUT) value is lower than a predetermined voltage value of the power supply, the voltage detector will issue a signal to drive the second transistor and limit a gate-source voltage (VGS) of the first transistor within a voltage difference of the diode, so as to reduce the impetus of the first transistor and avoid the phenomenon of a sudden climb with an excessively large output voltage (VOUT).Type: GrantFiled: October 28, 2005Date of Patent: January 15, 2008Assignee: Phison Electronics Corp.Inventors: Wee-Kuan Gan, Chih-Jen Hsu
-
Publication number: 20080010397Abstract: The invention presents a multi-type flash memory with simulating system and a method thereof. Meanwhile the method includes the steps of a) providing a simulating circuit data for the multi-type flash memory; b) transforming the simulating circuit data into a programmable circuit device; c) connecting a flash memory access interface of the multi-type flash memory with a first host system; d) connecting a large-scale access interface of the multi-type flash memory with a second host system; e) transmitting data signals between a buffer register of the multi-type flash memory and the first/second host systems via the flash memory access interface/the large-scale access interface; and f) transmitting control signal between the buffer register and the first/second host systems via the programmable circuit device and the flash memory access interface/the large-scale access interface, thereby incorporating a simulating system into the multi-type flash memory conveniently.Type: ApplicationFiled: July 10, 2006Publication date: January 10, 2008Applicant: Phison Electronics Corp.Inventors: Jen-Chieh Lou, Chih-Jen Hsu
-
Publication number: 20080005449Abstract: The invention presents a flash memory with a generalized interface for facilitating to develop multi-type flash memories and a method thereof. Meanwhile the generalized flash memory includes a physical memory for storing data; a logical controller connected with the physical memory for providing an identify function of the physical memory and communicating with an external system in an unified format; and a buffer register connected with the logical controller, wherein the logical controller and the buffer register map the physical memory to an entire continuous memory space, thereby facilitating to develop multi-type flash memories.Type: ApplicationFiled: July 3, 2006Publication date: January 3, 2008Applicant: Phison Electronics Corp.Inventors: Jen-Chieh Lou, Chih-Jen Hsu
-
Publication number: 20070266297Abstract: A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the controller both writes all 0×FF data in the data area and writes all 0×FF error-correcting codes in the error-correcting code area, the first inverting circuit inverts the all 0×FF data and the all 0×FF error-correcting codes into all 0×00 data and all 0×00 error-correcting codes, respectively.Type: ApplicationFiled: June 5, 2007Publication date: November 15, 2007Applicant: PHISON ELECTRONICS CORP.Inventors: Ming-Jen Liang, Wee-Kuan Gan, Chih-Jen Hsu
-
Patent number: 7276889Abstract: A detect/modulate circuit comprises a plurality of modulate resistors connected to a main resistor of a bandgap in series, and each module resistor is connected to a transistor switch in parallel, and each transistor switch is connected to a logic controller, and the logic controller is connected in sequence to a plurality of detect circuits and fuses corresponding to the quantity of the transistor switches. When the detect circuit receives a low-to-high power-on reset signal to detect whether or not the fuse is fused, the detect circuit will issue a voltage level signal “0” for the fuse being not fused or a voltage level signal “1” for the fuse being fused to the logic controller. The logic controller converts the received voltage level signal according to a logic conversion table to control the electric connection of the corresponding transistor switch, so as to fine turn the main resistance of the bandgap.Type: GrantFiled: October 21, 2005Date of Patent: October 2, 2007Assignee: Phison Electronics CorporationInventors: Wee-Kuan Gan, Chih-Jen Hsu
-
Patent number: 7263649Abstract: A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0xFF data into the flash memory, the byte error correction rule generates a set of correct error correction codes and the error correction code converting circuit converts the set of correct error correction codes into 0xFF error correction codes, and values stored in the data area and error correction code area of the flash memory are converted into 0xFF to prevent wrong error correction code from occurring during data reading operation when the error correction codes are not completely 0xFF.Type: GrantFiled: August 9, 2004Date of Patent: August 28, 2007Assignee: Phison Electronics CorporationInventors: Wee-Kuan Gan, Chih-Jen Hsu
-
Publication number: 20070090823Abstract: A detect/modulate circuit comprises a plurality of modulate resistors connected to a main resistor of a bandgap in series, and each module resistor is connected to a transistor switch in parallel, and each transistor switch is connected to a logic controller, and the logic controller is connected in sequence to a plurality of detect circuits and fuses corresponding to the quantity of the transistor switches. When the detect circuit receives a low-to-high power-on reset signal to detect whether or not the fuse is fused, the detect circuit will issue a voltage level signal “0” for the fuse being not fused or a voltage level signal “1” for the fuse being fused to the logic controller. The logic controller converts the received voltage level signal according to a logic conversion table to control the electric connection of the corresponding transistor switch, so as to fine turn the main resistance of the bandgap.Type: ApplicationFiled: October 21, 2005Publication date: April 26, 2007Applicant: PHISON ELECTRONICS CORP.Inventors: Wee-Kuan Gan, Chih-Jen Hsu
-
Publication number: 20070011225Abstract: A multimedia player is disclosed. The multimedia player comprises a host end and a receiving end. The host end comprises a transmission interface, a wireless transmission interface and a host connected to the transmission interface and the wireless transmission interface. The transmission interface is adopted for connecting to the Internet for downloading and transmitting a multimedia entertainment content. The receiving end comprises a microcontroller connected to a wireless transmission interface adopted for receiving the multimedia entertainment content transmitted from the wireless transmission interface of the host end, and a digital/analog converter for converting the multimedia entertainment content into a playable format for a playing device. The microcontroller and the digital/analog converter are connected to a monitor and said playing device respectively.Type: ApplicationFiled: July 7, 2005Publication date: January 11, 2007Applicant: PHISON ELECTRONICS CORP.Inventors: Chih-Jen Hsu, Sheng-Yu Chang
-
Publication number: 20060267673Abstract: The present invention describes a modulator including a differential amplifier connected to a reference voltage and a first transistor, and the first transistor is connected to a feedback device, and a second transistor is set between the first transistor and the differential amplifier and connected to a voltage detector and a diode, and the diode is connected to a power supply, and the voltage detector keeps on detecting an output voltage (VOUT) between the feedback device and the first transistor. If the output voltage (VOUT) value is lower than a predetermined voltage value of the power supply, the voltage detector will issue a signal to drive the second transistor and limit a gate-source voltage (VGS) of the first transistor within a voltage difference of the diode, so as to reduce the impetus of the first transistor and avoid the phenomenon of a sudden climb with an excessively large output voltage (VOUT).Type: ApplicationFiled: October 28, 2005Publication date: November 30, 2006Applicant: PHISON ELECTRONICS CORP.Inventors: Wee-Kuan Gan, Chih-Jen Hsu
-
Publication number: 20060136788Abstract: A test system including a generating unit, a knowledge base, a collecting unit and a determining unit is provided. The generating unit is for generating a test case according to a test plan. The knowledge base is for providing a test item and a corresponding checking method according the test plan. The collecting unit is for collecting the system information from a device under test. The determining unit is for checking whether the system information has the test item according the checking method. And whether the test item passes or fails is determined by the determining unit according. the checking result.Type: ApplicationFiled: November 22, 2005Publication date: June 22, 2006Inventors: Chih-Jen Hsu, Dar-Lun Chen