Patents by Inventor Chih-Jen Huang
Chih-Jen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968038Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.Type: GrantFiled: July 19, 2021Date of Patent: April 23, 2024Assignee: Cisco Technology, Inc.Inventors: Keerthi Manjunathan Swarnamanjunathan, Chih-Tsung Huang, Kelvin Chan, Wei-Jen Huang
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Publication number: 20240126002Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.Type: ApplicationFiled: October 2, 2023Publication date: April 18, 2024Applicant: Coretronic CorporationInventors: Chih-Jen Tsang, Chung-Wei Huang, Shih-Yen Cheng, Jung-Wei Chang, Han-Yuan Liu, Chun-Wei Lee
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Publication number: 20240106737Abstract: The present technology is directed to a system and method for application aware management and recovery of link failures resulting from excessive errors observed on the link. One aspect of the proposed technology is based on identification of link errors associated with application-specific data patterns traversing link. Other aspects involve corrective actions based on relocation or modification of specific application traffic to thereby alleviate the observed excessive link errors and prevent a link failure or shut down. Relocation may involve moving the source application to a different virtual machine/container/physical device or rerouting application traffic by updating relevant routing protocols. Modification may involve harmlessly changing payload data pattern to remove data-pattern dependent signal attenuation.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Inventors: Chih-Tsung Huang, Wei-Jen Huang
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11933999Abstract: An optical structure film and a light source module are provided. The optical structure film includes multiple optical unit microstructures. Each of the optical unit microstructures has four side surfaces and an inwardly concave beam splitting surface. The beam splitting surface is respectively connected to the side surfaces, and the beam splitting surface has four endpoints when viewed from a front viewing angle. Connection lines of the four endpoints form a rectangle. The beam splitting surface includes at least one beam splitting curved surface. A junction of the at least one beam splitting curved surface and one of the four side surfaces is a first line segment. A projection of a midpoint of an edge of the rectangle on the beam splitting surface overlaps with a relative extreme point of the first line segment.Type: GrantFiled: December 1, 2022Date of Patent: March 19, 2024Assignee: Coretronic CorporationInventors: Wen-Chun Wang, Chih-Jen Tsang, Chung-Wei Huang
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Publication number: 20240087861Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
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Publication number: 20230332730Abstract: According to an example, a display mount comprises a mount base to attach to a work surface, a body member having a first lateral side lateral to and wider than a second side, and a movable member to receive the body member. The movable member comprises a support element to attach to a display and a locking mechanism aligned with the second side of the body member and movable between an unlocked position in which the movable member is movable along a length of the body member and a locked position in which the locking mechanism fixes the movable member with respect to the body member.Type: ApplicationFiled: April 13, 2022Publication date: October 19, 2023Inventors: Hung-Chang CHEN, Hai-Lung HUNG, Chih Jen HUANG
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Patent number: 11755758Abstract: Various embodiments provide processes for identification of embedded unauthorized data within document data. Such processes may include evaluating document data properties for indications of closing headers, comparing document data sizes against reference sizes, and comparing document data sizes against other document data sizes. Certain embodiments evaluating image data may evaluate image properties, such as histograms or gradient images, to determine random or otherwise unauthorized data. Upon detection of unauthorized data, the document data may be flagged for later processing, such as removal from a storage server.Type: GrantFiled: October 30, 2017Date of Patent: September 12, 2023Assignee: Amazon Technologies, Inc.Inventors: Scott Southwood, Canku Alp Calargun, Brett Lounsbury, Prajwal Yadapadithaya, Ankit Garg, Chih-Jen Huang, Vivek Chaganti
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Publication number: 20230148003Abstract: A memory device and a method of manufacturing the same are provided. The memory device includes a substrate, a memory cell array, and a memory cell interconnection structure. The memory cell array is disposed on the substrate and includes a plurality of memory cells. Each of the plurality of memory cells includes a transistor unit and a memory unit that are electrically connected to each other. The memory cell interconnection structure is disposed on the substrate, and is configured to establish an electrical connection between the plurality of memory cells. A plurality of source lines are embedded in a dielectric layer that directly covers the substrate. Each of the plurality of source lines is disposed on the substrate, and comes in direct contact with a source region of a corresponding one of the transistor units.Type: ApplicationFiled: November 2, 2022Publication date: May 11, 2023Inventors: CHAO-YANG CHEN, CHIH-JEN HUANG
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Publication number: 20230143211Abstract: A memory device and a method of manufacturing the same are provided. The memory device includes a substrate, a memory cell array, and a memory cell interconnection structure. The memory cell array is disposed on the substrate. Each memory cell in the memory cell array includes a transistor unit and a memory unit that are electrically connected to each other. The memory cell interconnection structure is configured to establish an electrical connection between the memory cells, and includes a dielectric layer and a plurality of drain conductive structures. At least one drain conductive pillar includes a first contact portion and a second contact portion that are connected to each other and embedded in the dielectric layer. One side surface of the first contact portion is recessed along a first direction with respect to one side surface of the second contact portion, so as to form a stepped structure.Type: ApplicationFiled: October 28, 2022Publication date: May 11, 2023Inventors: CHAO-YANG CHEN, CHIH-JEN HUANG
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Patent number: 11063824Abstract: A peer-to-peer (P2P) network boost system for boosting the transmission of specific packets between at least two electronic devices on the internet includes at least one boosting node and a hardware boosting device, wherein the hardware boosting device includes a geographical location judging module, a P2P matching module and a transmitting module. The boosting node is configured for receiving the specific packets and planning the transmitting route of the specific packet. The hardware boosting device judges the specific packets from a plurality of packets sent by the electronic device and sends the specific packets to the others electronic devices through the boosting node. The P2P network boost system achieves the network boosting function and optimizes the transmitting route through the hardware boosting device and the boosting node to improve the connecting quality and reduce the connecting cost.Type: GrantFiled: March 13, 2020Date of Patent: July 13, 2021Assignee: FORGAMERS INC.Inventors: Chih-Jen Huang, Yu-Hsiang Wu
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Patent number: 11017876Abstract: A memory correcting method includes steps: providing a memory with a plurality of memory bytes; respectively adding a plurality of correcting bytes to the plurality of memory bytes; providing a plurality of non-volatile compared memory bytes; detecting whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory bytes of the memory to complete the correction. Alternatively, the method respectively provides a plurality of compared memory address bytes for the plurality of memory bytes and for the plurality of correcting bytes for labeling underperforming-bit addresses. Then, the method detects whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory address bytes of the memory to complete the correction.Type: GrantFiled: November 18, 2019Date of Patent: May 25, 2021Assignee: 2X Memory Technology Corp.Inventor: Chih-Jen Huang
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Patent number: 10840343Abstract: A semiconductor structure for a wide bandgap normally off MOSFET has a III-group nitride, a V-group nitride, or a high K material trapping layer disposed under a gate electrode. Through the FN tunneling effect or channel hot electron (CHE) effect, multiple electrons are trapped by the trapping layer and kept in the trapping layer. The electrons in the trapping layer deplete the two-dimensional electron gas (2DEG) below the trapping layer, and then the 2DEG below the gate electrode disappear.Type: GrantFiled: November 1, 2019Date of Patent: November 17, 2020Inventor: Chih-Jen Huang
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Patent number: 10833794Abstract: A data transmission boosting system includes a boosting server and a client boosting device, wherein the boosting server and the client boosting device are connected to the internet respectively. The client boosting device further includes a data receiving module, a classifying module, and a transmitting module. The data receiving module receives data packets from at least one terminal device. The classify module classifies the data packets as data packets to be boosted, non-boosting data packets, or unknown data packets. The transmitting module transmits the data packets classified as the data packets to be boosted to the boosting server through the internet, and transmits the data packets classified as the non-boosting data packets to the internet.Type: GrantFiled: May 3, 2019Date of Patent: November 10, 2020Assignee: FORGAMERS INC.Inventors: Chih-Jen Huang, Yu-Hsiang Wu, Ming-Tze Hung, Chih-Hsiu Hung
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Publication number: 20200295989Abstract: A peer-to-peer (P2P) network boost system for boosting the transmission of specific packets between at least two electronic devices on the internet includes at least one boosting node and a hardware boosting device, wherein the hardware boosting device includes a geographical location judging module, a P2P matching module and a transmitting module. The boosting node is configured for receiving the specific packets and planning the transmitting route of the specific packet. The hardware boosting device judges the specific packets from a plurality of packets sent by the electronic device and sends the specific packets to the others electronic devices through the boosting node. The P2P network boost system achieves the network boosting function and optimizes the transmitting route through the hardware boosting device and the boosting node to improve the connecting quality and reduce the connecting cost.Type: ApplicationFiled: March 13, 2020Publication date: September 17, 2020Applicant: FORGAMERS INC.Inventors: Chih-Jen HUANG, Yu-Hsiang WU
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Patent number: 10692575Abstract: A method for self-terminated writing with quasi-constant voltage drop across resistive-type memory cell is provided. The method comprises: creating a writing voltage and a writing current flowing through a resistive memory cell; reproducing the writing current to generate a reproduced writing current; flowing the reproduced writing current through a dummy circuit to generate a dummy writing voltage; adding the dummy writing voltage and a reference voltage to generate a reference writing voltage, wherein the dummy writing voltage slightly and proportionally increases during writing; and adjusting the writing voltage and the writing current according to the reference writing voltage so that a voltage drop across the resistive memory cell keeps constant or slightly increases during writing. When the reproduced writing current reaches a predetermined target current value, a termination signal is issued.Type: GrantFiled: March 28, 2019Date of Patent: June 23, 2020Assignee: 2X Memory Technology Corp.Inventor: Chih-Jen Huang
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Publication number: 20200195369Abstract: A data transmission boosting system includes a boosting server and a client boosting device, wherein the boosting server and the client boosting device are connected to the internet respectively. The client boosting device further includes a data receiving module, a classifying module, and a transmitting module. The data receiving module receives data packets from at least one terminal device. The classify module classifies the data packets as data packets to be boosted, non-boosting data packets, or unknown data packets. The transmitting module transmits the data packets classified as the data packets to be boosted to the boosting server through the internet, and transmits the data packets classified as the non-boosting data packets to the internet.Type: ApplicationFiled: May 3, 2019Publication date: June 18, 2020Inventors: Chih-Jen HUANG, Yu-Hsiang WU, Ming-Tze HUNG, Chih-Hsiu HUNG
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Publication number: 20200195564Abstract: A data transmission boosting device which can receive a plurality of data packets generated by terminal devices and connect to the router. The data transmission boosting device includes a classifying module which stores a classifying model, and the classifying model includes a plurality of classifying features. The classifying module can classify the type of each data packets by the classifying model and the packet information of data packets. The data transmission boosting device transmits the data packets classified as the data packets for boosting to the boosting server through the router. The data transmission boosting device of the present invention not only can improve the transmission efficient by the classifying module, but also can save the network flow cost.Type: ApplicationFiled: May 1, 2019Publication date: June 18, 2020Inventors: Chih-Jen HUANG, Yu-Hsiang WU, Yi-Xuan LU
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Patent number: 10642686Abstract: A bit-scale memory correcting method comprises steps: providing a memory with a plurality of memory bytes each having M bits, wherein M is a positive integer; adding a correcting byte to each memory byte, wherein the correcting byte has N correcting bits, and wherein N is a positive integer and smaller than M; detecting whether there is any underperforming bit in all the memory bytes and correcting bytes; if no, terminating memory correction; if yes, using the non-underperforming bits of the correcting byte to replace the underperforming bits of the memory byte, wherein the quantity of the non-underperforming bits of the correcting byte is corresponding to the quantity of the underperforming bits of the memory byte. The present invention proposes a simple and fast memory bit correcting method to decrease the redundant bits for correcting memory bits.Type: GrantFiled: January 12, 2018Date of Patent: May 5, 2020Assignee: TARGPS TECHNOLOY CORP.Inventor: Chih-Jen Huang