Abstract: In a LED driver, a diming control circuit receives a PWM signal and a clock signal and outputs a dimming signal and a sampling signal. A turn-on time of sampling signal is shorter than a cycle of clock signal. A first error amplifier receives a feedback voltage, a reference voltage and a dimming signal and outputs a compensating voltage. A second error amplifier receives the compensating voltage and a ramp signal and outputs a pulse voltage. A driving controller receives the dimming signal and pulse voltage and outputs a control signal. An output stage receives the control signal and an input voltage and generates an output voltage to LED strings. A minimum voltage selecting unit selects a minimum LED voltage. The first error amplifier receives the minimum LED voltage through the selectively conducted switch unit controlled by the sampling signal.

Abstract: A driving chip set includes a master chip and at least one slave chip. In the master chip, a master receiving terminal receives a data signal through a first data transmission interface; a processing unit generates a first partial data signal and a second partial data signal according to the data signal; a master buffer registers the first partial data signal; a master output terminal outputs the second partial data signal through a second data transmission interface. In the slave chip, a slave receiving terminal receives the second partial data signal through the second data transmission interface and it is registered by a slave buffer. The processing unit controls a master driver and a slave driver to output the first partial data signal and second partial data signal to a display panel. The display panel displays an image according to the first partial data signal and second partial data signal.

Abstract: A driving chip set includes a master chip and at least one slave chip. In the master chip, a master receiving terminal receives a data signal through a first data transmission interface; a processing unit generates a first partial data signal and a second partial data signal according to the data signal; a master buffer registers the first partial data signal; a master output terminal outputs the second partial data signal through a second data transmission interface. In the slave chip, a slave receiving terminal receives the second partial data signal through the second data transmission interface and it is registered by a slave buffer. The processing unit controls a master driver and a slave driver to output the first partial data signal and second partial data signal to a display panel. The display panel displays an image according to the first partial data signal and second partial data signal.

Abstract: A heat detector for a main board at least comprises a current generation unit, a heat perception element, and an analog to digital converter (ADC). The current generation unit generates at least one current signal. The heat perception element electrically connects to the current generation unit and generates an analog signal according to the current signal. The ADC electrically connects to the current generation unit and the heat perception element. The ADC is for converting the analog signal into a digital signal.

Abstract: An oscillator circuit includes an electrical load, a first metal oxide semiconductor (MOS) devise, a second MOS device, and a negative feedback circuit. The electrical load is coupled between a first node and a second node. The first MOS device is coupled between the first node and a third node, and controls a first current flowing from the first node to the third node. The second MOS device is coupled between the second node and a fourth node, and controls a second current flowing from the second node to the fourth node. A positive feedback circuit is formed with the first and second MOS devices. The positive feedback circuit has inputs from the first and second nodes and outputs to the first and second MOS devices. The negative feedback circuit has inputs from the third and fourth nodes and outs to the first and second MOS devices.

Abstract: A circuit includes a switched-capacitor array for converting a digital signal into a corresponding amount of electric charge, a switching circuit, and a continuous-time reconstruction filter circuit. The switched-capacitor array includes a plurality of capacitors and a summing node to which the plurality of capacitors are connected. The switching circuit is coupled between the summing node and the continuous-time reconstruction filter circuit, and supplies a pulsed current signal to the continuous-time reconstruction filter circuit. The circuit may further include a gain stage coupled between the summing node and the switching circuit, for controlling a gain of the pulsed current signal. The gain stage may include a coupling capacitor. A digital signal is supplied to the switched capacitor array and converted into a corresponding amount of electric charge. The electric charge is supplied as a pulsed current signal to the continuous-time reconstruction filter circuit without converting into a voltage signal.