Abstract: The disclosure provides a finger type antenna, including a short-circuit portion, a feeding portion, an open-circuit portion, a ground portion, and a coplanar waveguide. The short-circuit portion has a first end and a second end. The feeding portion has a first end and a second end, wherein the first end of the feeding portion is coupled to the first end of the short-circuit portion. The open-circuit portion includes at least three antenna elements, wherein each antenna element has a first end and a second end, and the first ends of the antenna elements are coupled to each other via the feeding portion. The coplanar waveguide is connected to the second end of the short-circuit portion, the second end of the feeding portion, and the ground portion.

Abstract: A fluid detection apparatus and a fluid detection method are provided. The fluid detection apparatus includes a plurality of capacitive detection units and a sensing circuit. The capacitive detection units are sequentially arranged along a detection direction, wherein each of the capacitive detection units generates an impedance variation in response to the submergence of the fluid and accordingly generates a corresponding fluid detection signal. The sensing circuit is coupled to the capacitive detection units so as to receive the fluid detection signals and send a first status indication signal indicating a spread circumstance of the fluid along the detection direction according to the fluid detection signals.

Abstract: A fluid detection apparatus and a fluid detection method are provided. The fluid detection apparatus includes a plurality of capacitive detection units and a sensing circuit. The capacitive detection units are sequentially arranged along a detection direction, wherein each of the capacitive detection units generates an impedance variation in response to the submergence of the fluid and accordingly generates a corresponding fluid detection signal. The sensing circuit is coupled to the capacitive detection units so as to receive the fluid detection signals and send a first status indication signal indicating a spread circumstance of the fluid along the detection direction according to the fluid detection signals.

Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.

Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.

Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.

Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.

Abstract: A universal serial bus (USB) with single port and a host controller thereof are provided. The USB comprises a USB port, a speed detection circuitry, a start of frame (SOF) generator, and a host controller. The USB port is electrically coupled to an external circuitry. The speed detection circuitry is electrically coupled to the USB port for detecting a transmission speed between the USB and the external circuitry via the USB port to provide a detecting result. The SOF generator is electrically coupled to the speed detection circuitry for receiving the detecting result and outputting a SOF signal, to determine a cycle of the SOF signal based on the detecting result. The host controller is electrically coupled to the SOF generator and the speed detection circuitry for adjusting the host controller based on SOF signal cycle to comply with the USB 2.0, USB 1.1 and USB 1.0 transmission standards.

Abstract: A universal serial bus (USB) with single port and a host controller thereof are provided. The USB comprises a USB port, a speed detection circuitry, a start of frame (SOF) generator, and a host controller. The USB port is electrically coupled to an external circuitry. The speed detection circuitry is electrically coupled to the USB port for detecting a transmission speed between the USB and the external circuitry via the USB port to provide a detecting result. The SOF generator is electrically coupled to the speed detection circuitry for receiving the detecting result and outputting a SOF signal, to determine a cycle of the SOF signal based on the detecting result. The host controller is electrically coupled to the SOF generator and the speed detection circuitry for adjusting the host controller based on SOF signal cycle to comply with the USB 2.0, USB 1.1 and USB 1.0 transmission standards.

Abstract: A method and apparatus for transmitting registered data onto a PCI bus is provided, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit complexity. The apparatus employee a 2R1W data buffer to send a current phase data and a next phase data one clock cycle ahead of the actual AD activity on PCI bus and use a multiplexer to select the current phase data or the next phase data according to a select signal. The select signal is outputted by a OR gate with IRDY# and TRDY# signals as its inputs. Then, the apparatus use a flip-flop to toggling the output signal of the multiplexer to the PCI bus at the actual AD activity. Therefore, the apparatus of the present invention not only reduce the delay time of manipulating the outgoing signals, but also is implemented with simple architecture.