Patents by Inventor Chih-Ju CHANG

Chih-Ju CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11995471
    Abstract: A resource integration method includes the following steps: a receiving module receives access information from a guest operating system on the host device; the access information is used to determine whether the frame rate is lower than a frame rate threshold; when the receiving module determines that the frame rate is lower than the frame rate threshold, the receiving module transmits an external resource request signal to the receiving module; after the receiving module receives the external resource request signal, a resource management module (which is located in the bridge module) selects an optimal external device from a specific category (among a plurality of categories in a candidate list), and a calculation operation or a storage operation corresponding to the specific category is transmitted to the optimal external device for calculation or storage by the bridge module.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: May 28, 2024
    Assignee: ACER INCORPORATED
    Inventors: Kuan-Ju Chen, Wen-Cheng Hsu, Hung-Ming Chang, Chih-Wen Huang, Chao-Kuang Yang
  • Patent number: 11942652
    Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: March 26, 2024
    Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chen-Ting Kao, Chi-Cheng Wen, Yu-Sheng Chang, Chih-Cheng Lee, Chiung-Hsiang Wu, Sheng-Li Yen, Yu-Cheng Zhang, Chang-Ju Hsieh, Chen Chao
  • Publication number: 20240087961
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Ju CHOU, Chih-Chung Chang, Jun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Kao, Chen-Hsuan Liao
  • Patent number: 11927303
    Abstract: A wearable device includes a host, a first belt, a second belt, a circuit board, a cable, and an adjustment mechanism. The first belt, one end of which is connected to a first side of the host, has a cable holding part. One end of the second belt is connected to a second side of the host. The circuit board is disposed at an overlap of the first belt and the second belt. A first end and a second end opposite to each other of the cable are connected to the circuit board and the first side respectively, and a holding section of the cable is fixed to the cable holding part. The adjusting mechanism is disposed at an overlap of the first belt and the second belt to adjust an overlapping length of the first belt and the second belt.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 12, 2024
    Assignee: HTC Corporation
    Inventors: Tsen-Wei Kung, Chung-Ju Wu, Tsung Hua Yang, Chih-Yao Chang, Wei Te Tu
  • Patent number: 11929258
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20240077914
    Abstract: A foldable electronic device includes a first body having an end and a first inclined surface, a second body having a second inclined surface, and a hinge module. The end includes an accommodating area. A virtual shaft line exists between sides of the first inclined surface and the second inclined surface that are closest to each other. The second body rotates relative to the first body through the virtual shaft line. The hinge module includes a first bracket adjacent to the first inclined surface, connected to the first body, and located in the accommodating area, a second bracket adjacent to the second inclined surface and connected to the second body, and a third bracket including a first end and a second end. The first bracket is connected to the first end through a first torsion assembly. The second bracket is connected to the second end through a second torsion assembly.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chih-Han Chang, Tsung-Ju Chiang, Chi-Hung Lin, Yen-Ting Liu
  • Patent number: 11923250
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Patent number: 8891844
    Abstract: A time synchronization calibration method and system for image taking and coordinate reading and a delay time calculation method thereof are disclosed. The time synchronization calibration method is as follows. Firstly, every time point, a calibrator coordinate, an operation target coordinate and an image thereof are obtained. The image similarity index of every image and the image of previous time point thereof is calculated. When the image similarity index is lower than a preset similarity index, a reading time of the image is output followed with calculating the difference of the reading time and a time delay to obtain a taking time of the image. Finally, calculating the coordinate transformation of the calibrator coordinate and the operation target coordinate, and corresponding it to the image to output an image-coordinate correspondence relation. The time delay can be obtained correctly with only one test, and provided for the consequent synchronization calibration.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 18, 2014
    Assignee: National Central University
    Inventors: Ching-Shiow Tseng, Alex Tse, Chih-Ju Chang
  • Publication number: 20140133730
    Abstract: A time synchronization calibration method and system for image taking and coordinate reading and a delay time calculation method thereof are disclosed. The time synchronization calibration method is as follows. Firstly, every time point, a calibrator coordinate, an operation target coordinate and an image thereof are obtained. The image similarity index of every image and the image of previous time point thereof is calculated. When the image similarity index is lower than a preset similarity index, a reading time of the image is output followed with calculating the difference of the reading time and a time delay to obtain a taking time of the image. Finally, calculating the coordinate transformation of the calibrator coordinate and the operation target coordinate, and corresponding it to the image to output an image-coordinate correspondence relation. The time delay can be obtained correctly with only one test, and provided for the consequent synchronization calibration.
    Type: Application
    Filed: March 8, 2013
    Publication date: May 15, 2014
    Applicant: NATIONAL CENTRAL UNIVERSITY
    Inventors: Ching-Shiow TSENG, Alex TSE, Chih-Ju CHANG
  • Patent number: D1026916
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee