Patents by Inventor Chih-Jui Peng
Chih-Jui Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9830418Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.Type: GrantFiled: October 27, 2015Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ray Chih-Jui Peng
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Publication number: 20160048626Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.Type: ApplicationFiled: October 27, 2015Publication date: February 18, 2016Inventor: Ray Chih-Jui Peng
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Patent number: 9172377Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.Type: GrantFiled: April 2, 2015Date of Patent: October 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ray Chih-Jui Peng
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Publication number: 20150214951Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.Type: ApplicationFiled: April 2, 2015Publication date: July 30, 2015Inventor: Ray Chih-Jui Peng
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Patent number: 9007094Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.Type: GrantFiled: February 25, 2013Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ray Chih-Jui Peng
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Patent number: 8384436Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.Type: GrantFiled: January 10, 2011Date of Patent: February 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ray Chih-Jui Peng
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Publication number: 20120176157Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.Type: ApplicationFiled: January 10, 2011Publication date: July 12, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ray Chih-Jui Peng
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Patent number: 7793015Abstract: Methods and apparatus for rate control are provided. An isochronous circuit controls data transmission between a first device and a second device. The first device outputs a set of data packets to the isochronous circuit at a first data rate, and the second device pulls the set of data packets from the isochronous circuit at a second data rate. The isochronous circuit comprises a buffer, a rate calculator and a register. The buffer buffers the set of data packets bound to the second device through a USB. The rate calculator monitors occupation of the buffer to estimate the second data rate. The register is coupled to the rate calculator for storage of the second data rate. The first device may access the estimate of the second data rate from the register to update the first data rate.Type: GrantFiled: March 27, 2008Date of Patent: September 7, 2010Assignee: Fortemedia, Inc.Inventors: Tsung-Hsien Hsieh, Ray Chih-Jui Peng
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Publication number: 20090245446Abstract: Methods and apparatus for rate control are provided. An isochronous circuit controls data transmission between a first device and a second device. The first device outputs a set of data packets to the isochronous circuit at a first data rate, and the second device pulls the set of data packets from the isochronous circuit at a second data rate. The isochronous circuit comprises a buffer, a rate calculator and a register. The buffer buffers the set of data packets bound to the second device through a USB. The rate calculator monitors occupation of the buffer to estimate the second data rate. The register is coupled to the rate calculator for storage of the second data rate. The first device may access the estimate of the second data rate from the register to update the first data rate.Type: ApplicationFiled: March 27, 2008Publication date: October 1, 2009Applicant: FORTEMEDIA, INC.Inventors: Tsung-Hsien Hsieh, Ray Chih-Jui Peng
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Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline
Patent number: 6633971Abstract: A method for forwarding data within a pipeline of a pipelined data processor having a plurality of execution pipeline stages where each stage accepts a plurality of operand inputs and generates a result. The result generated by each execution pipeline stage is selectively coupled to an operand input of one of the execution pipeline stages.Type: GrantFiled: October 1, 1999Date of Patent: October 14, 2003Assignee: Hitachi, Ltd.Inventors: Chih-Jui Peng, Lew Chua-Eoan -
Publication number: 20030154364Abstract: A method for forwarding data within a pipeline of a pipelined data processor having a plurality of execution pipeline stages where each stage accepts a plurality of operand inputs and generates a result. The result generated by each execution pipeline stage is selectively coupled to an operand input of one of the execution pipeline stages.Type: ApplicationFiled: October 1, 1999Publication date: August 14, 2003Inventors: CHIH-JUI PENG, LEW CHUA-EOAN
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Patent number: 6542983Abstract: In a computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU execution pipeline including a CPU decoder pipestage and the FPU execution pipeline including an FPU decoder pipestage, the method including the steps of, (a) sending a first instruction to the CPU decoder pipestage, (b) sending the first instruction to the FPU decoder pipestage, (c) generating a signal indicating that the first instruction has been accepted by the CPU decoder pipestage, (d) generating a signal indicating that the first instruction has been accepted by the FPU decoder pipestage, (e) sending a second instruction to the CPU decoder pipestage in response to step (d), and (f) sending a second instruction to the FPU decoder pipestage in response to step (c). A corresponding apparatus is also provided.Type: GrantFiled: October 1, 1999Date of Patent: April 1, 2003Assignee: Hitachi, Ltd.Inventors: Margaret Rose Gearty, Chih-Jui Peng
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Patent number: 6477638Abstract: A computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU pipeline including a plurality of pipestages and the FPU pipeline including a plurality of pipestages, wherein each CPU pipestage in the CPU pipeline has a corresponding pipestage in the FPU pipeline, a method of synchronizing operation of the CPU pipeline and the FPU pipeline, the method including the steps of (a) receiving an instruction in a first CPU pipestage, (b) receiving the instruction in a corresponding first FPU pipestage, (c) processing the instruction in the first CPU pipestage, (d) processing the instruction in the first FPU pipestage, (e) generating, by the first CPU pipestage, a first signal indicating that the instruction has been processed by first CPU pipestage and is ready to proceed to a second pipestage in the CPU pipeline, (f) generating by the first FPU pipestage, a second signal indicating that the instruction has been processed by the first FPU pipesType: GrantFiled: October 1, 1999Date of Patent: November 5, 2002Assignee: Hitachi, Ltd.Inventors: Margaret Rose Gearty, Chih-Jui Peng
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Publication number: 20020161985Abstract: A computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU pipeline comprising a plurality of pipestages and the FPU pipeline comprising a plurality of pipestages wherein each CPU pipestage has a corresponding pipestage in the floating point unit FPU pipeline, a method of synchronizing operation of the CPU pipeline and the FPU pipeline, the method including the steps of (a) providing instructions to each pipestage in the CPU pipeline, (b) providing the instructions to each corresponding pipestage in the FPU pipeline, (c) executing the instructions in the CPU pipeline, (d) executing the instructions in the FPU pipeline, (e) stalling the CPU pipeline in response to a stall condition, (f) stalling the FPU unit pipeline a predetermined number of pipestages after the CPU pipeline has stalled, (g) storing the state of execution of the floating point processing unit pipeline in response to step (f), (h) removing the stall condition and restType: ApplicationFiled: October 1, 1999Publication date: October 31, 2002Inventors: Margaret Rose Gearty, Chih-Jui Peng
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Patent number: 6457118Abstract: According to the present invention, techniques for setting selected operand fields in pipelined architectures are provided. Methods and systems for efficiently selecting operand fields according to the present invention can be operative on a variety of computer architectures, including RISC architectures.Type: GrantFiled: October 1, 1999Date of Patent: September 24, 2002Assignee: Hitachi LTDInventors: Chih-Jui Peng, Glenn Ashley Farrall, Sivaram Krishnan
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Patent number: 6449712Abstract: A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.Type: GrantFiled: October 1, 1999Date of Patent: September 10, 2002Assignee: Hitachi, Ltd.Inventors: Naohiko Irie, Tony Lee Werner, Chih-Jui Peng, Sebastian H. Ziesler, Jackie A. Freeman, Sivaram Krishnan
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Patent number: 6408381Abstract: A method for low latency access to the control space. A pipeline processor executes instructions in multiple stages including a decode stage, one or more execution, stages, and a writeback stage. A control space access instruction includes a first field containing a control register specifier and a second field containing a general purpose register specifier. The decode stage is configured to decode the first and second fields and place the decoded contents on a global operand bus. The specified control register is addressed from the global operand bus while the access instruction is in decode. In the case of a read instruction, the addressed control register places its contents on the global operand bus while the instruction remains in decode.Type: GrantFiled: October 1, 1999Date of Patent: June 18, 2002Assignee: Hitachi, Ltd.Inventors: Margaret Gearty, Chih-Jui Peng
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Patent number: 6393523Abstract: A processor having an execution pipeline and a cache memory including a plurality of cache blocks with instruction words held in selected ones of the cache blocks. An ICBI address buffer is provided for holding addresses of instruction cache blocks to be invalidated by ICBI instructions pending in the processor's execution pipeline. An instruction cache controller coupled to the cache memory generates cache accesses to invalidate specified cache blocks in response to receiving buffered addresses from the ICBI address buffer. Preferably the cache accesses serve to commit ICBI instructions to the instruction cache asynchronously with respect to the processor's execution pipeline.Type: GrantFiled: October 1, 1999Date of Patent: May 21, 2002Assignee: Hitachi Ltd.Inventors: Chih-Jui Peng, Margaret Gearty, Naohiko Irie, Tony L. Werner
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Publication number: 20020056034Abstract: A data processing system including a memory system and a plurality of peripheral components. A processor is coupled to the memory and peripheral components. A plurality of pipeline stages are implemented within the processor where each stage is configured to perform specific operations according to instructions then associated with that stage. A snapshot register is associated with at least some of the pipeline stages where the snapshot register configured to store data describing the state of execution of the instruction then associated with that stage.Type: ApplicationFiled: October 1, 1999Publication date: May 9, 2002Inventors: MARGARET GEARTY, CHIH-JUI PENG
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Patent number: 6351803Abstract: A processor including a plurality of execution pipeline stages where each stage accepts a plurality of operand inputs and generates a result. A pipefile having at least the same number of entries as the number of execution pipeline stages is included in the processor. A pointer register is associated with each execution pipeline stage. A value is stored in at least one of the pointer registers, the value indicating a particular one of the entries in the pipefile.Type: GrantFiled: October 1, 1999Date of Patent: February 26, 2002Assignee: Hitachi Ltd.Inventors: Chih-Jui Peng, Lew Chua-Eoan