Abstract: A method for manufacturing a flash memory device is provided. The method includes forming a plurality of isolation structures in a substrate, an opening is formed between two adjacent isolation structures, and conformally depositing a first silicon seed layer on the substrate and the isolation structures and performing a first cycle. The first cycle includes performing a first deposition process to conformally form a first amorphous silicon layer on the first silicon seed layer. A first recess is defined by the first amorphous silicon layer. A first in-situ chlorine etching process is performed to widen the caliber of the first recess. The method includes performing a first thermal annealing process to transform the first amorphous silicon layer into a first polysilicon layer. The method includes performing an amorphous silicon deposition process to form an amorphous silicon layer on the first polysilicon layer and completely fill the opening.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.

Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.

Abstract: The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.

Abstract: Provided is a patterning method including following steps. A doped polysilicon layer, a core layer, and an undoped polysilicon layer are sequentially formed on a target layer. The undoped polysilicon layer are patterned to form a polysilicon pattern. A first etching process is performed by using the polysilicon pattern as a mask to remove a portion of the core layer to form a core pattern. A second etching process is performed to remove the polysilicon pattern. An atomic layer deposition (ALD) process is performed to form a spacer material on the core pattern and the doped polysilicon layer. A portion of the spacer material is removed to form a spacer on a sidewall of the core pattern. A portion of the core pattern and an underlying doped polysilicon are removed.

Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

Abstract: The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.

Abstract: A method for fabricating shallow trench isolation structures is provided. A patterned pad layer and a patterned mask layer are sequentially formed on a substrate, wherein the substrate includes a memory region and a periphery region. By using the patterned mask layer as a mask, the substrate is partially removed to form a plurality of trenches. A first liner layer is formed on the substrate to cover surfaces of the patterned mask layer, the patterned pad layer and the trenches. After removing the first liner layer in the periphery region, a pull-back process is performed on the patterned mask layer, and a pull-back amount of the patterned mask layer in the periphery region is larger than a pull-back amount of the patterned mask layer in the memory region. An insulating layer is formed in the trenches to form a plurality of shallow trench isolation structures.

Abstract: A method of forming a bonding pad opening is provided. A passivation layer and a mask layer are sequentially formed on a substrate having a bonding pad formed thereon. Thereafter, the passivation layer is etched to form an opening with use of an anti-reflection coating (ARC) layer of the bonding pad as an etching stop layer. Next, a dry removal process is performed to remove the mask layer. Afterwards, a wet cleaning process is performed to remove the residual mask layer or a polymer produced by previous manufacturing processes. Thereafter, the ARC layer is removed through performing an etching process with use of the passivation layer as a hard mask layer, so as to form the bonding pad opening.

Abstract: A method of forming a bonding pad opening is provided. A passivation layer and a mask layer are sequentially formed on a substrate having a bonding pad formed thereon. Thereafter, the passivation layer is etched to form an opening with use of an anti-reflection coating (ARC) layer of the bonding pad as an etching stop layer. Next, a dry removal process is performed to remove the mask layer. Afterwards, a wet cleaning process is performed to remove the residual mask layer or a polymer produced by previous manufacturing processes. Thereafter, the ARC layer is removed through performing an etching process with use of the passivation layer as a hard mask layer, so as to form the bonding pad opening.

Abstract: A method of manufacturing a gate dielectric layer is described. First, a substrate including a high voltage device region and a low voltage device region is provided. Plural isolation structures are formed in the substrate and protrude from the substrate. A high voltage gate dielectric layer is then formed on the substrate, and a passivation layer is formed on the high voltage gate dielectric layer in the high voltage device region. Next, a dry etching step is performed to remove a portion of the high voltage gate dielectric layer in the low voltage device region. Thereafter, a wet etching step is performed to remove the remaining high voltage gate dielectric layer in the low voltage device region. The passivation layer is then removed and a low voltage gate dielectric layer is formed on the substrate in the low voltage device region.

Abstract: A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide layer is disposed on the substrate. The floating gate is disposed on the tunnel oxide layer, and is constituted by a first conductive layer on the tunnel oxide layer and a second conductive layer on the first conductive layer. The second conductive layer has a bottom lower than the top surface of the first conductive layer, and has a bowl-like cross section. The insulating layer is disposed between the floating gates, and each control gate is disposed on a floating gate with an inter-gate dielectric layer between them.

Abstract: A method of spiking a mixed acid liquid in a reactor is performed under three modes of control, a based-on-charge mode control, a based-on-time mode control, and a based-on-time-and-charge mode control. In the based-on-charge mode control, spike timing and spiking amount of an acid liquid are set for each lot of product. In the based-on-time mode control, the spike timing and the spiking amount of the acid liquid are set for each timing point. In the based-on-time-and-charge mode control, the spike timing and the spiking amount of an acid liquid are set for each lot of product and each timing point. Thereby, a concentration of the mixed acid liquid is controlled at a targetlevel.

Abstract: A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide layer is disposed on the substrate. The floating gate is disposed on the tunnel oxide layer, and is constituted by a first conductive layer on the tunnel oxide layer and a second conductive layer on the first conductive layer. The second conductive layer has a bottom lower than the top surface of the first conductive layer, and has a bowl-like cross section. The insulating layer is disposed between the floating gates, and each control gate is disposed on a floating gate with an inter-gate dielectric layer between them.

Abstract: This application is about a method for removing the deep trench Si-needles on a wafer. The method includes steps of forming a photoresist layer on a frontside surface of the wafer, removing a specific area of the photoresist layer for exposing the Si-needles, proceeding a first etching and a second etching, and finally removing the photoresist layer on the frontside surface of the wafer. The first etching is a wet etching for removing the Si-needles by an etching solution etching from a backside surface of the wafer back to the frontside surface of the wafer. And, the second etching is a dry etching for removing the residual silicon nitride (SiN) slices formed during the first etching.

Abstract: This application is about a method for removing the deep trench Si-needles on a wafer. The method includes steps of forming a photoresist layer on a frontside surface of the wafer, removing a specific area of the photoresist layer for exposing the Si-needles, proceeding a first etching and a second etching, and finally removing the photoresist layer on the frontside surface of the wafer. The first etching is a wet etching for removing the Si-needles by an etching solution etching from a backside surface of the wafer back to the frontside surface of the wafer. And, the second etching is a dry etching for removing the residual silicon nitride (SiN) slices formed during the first etching.

Abstract: A method of spiking a mixed acid liquid in a reactor is performed under three modes of control, a based-on-charge mode control, a based-on-time mode control, and a based-on-time-and-charge mode control. In the based-on-charge mode control, spike timing and spiking amount of an acid liquid are set for each lot of product. In the based-on-time mode control, the spike timing and the spiking amount of the acid liquid are set for each timing point. In the based-on-time-and-charge mode control, the spike timing and the spiking amount of an acid liquid are set for each lot of product and each timing point. Thereby, a concentration of the mixed acid liquid is controlled at a targetlevel.

Abstract: A clean equipment for removing polymer residues on sidewalls of metal lines and method thereof are provided. The present clean equipment comprises a stripping solution bath, at least an organic solvent bath, an overflow bath and a dryer. A gas bubbler and a lattice-like cassette stage are positioned within the organic solvent bath. The gas bubbler provides gas flow in the organic solvent bath to increase the convection of the organic solvent. The lattice-like cassette stage is used for supporting cassettes for carrying wafers. By way of increasing the number of bubbling apertures of the gas bubbler and designing the gas bubbler structure in a way that preventing the bubbling apertures from being blocked by the lattice-like cassette stage, the convection effectiveness of the organic solvent is increased. Thereby, the stripping solution can be effectively removed with the organic solvent.