Abstract: A method is provided. The method includes introducing a process gas into an interior space of a processing chamber through a gas inlet port, wherein a substrate is supported within the interior space. The process gas is evacuated from the interior space by a vacuum source through an exhaust port in fluid communication with the interior space of the process chamber. A flow of the process gas is controlled by supporting an exhaust baffle within a flow path of the process gas being evacuated from the interior space through the exhaust port.

Abstract: A method is provided. The method includes introducing a process gas into an interior space of a processing chamber through a gas inlet port, wherein a substrate is supported within the interior space. The process gas is evacuated from the interior space by a vacuum source through an exhaust port in fluid communication with the interior space of the process chamber. A flow of the process gas is controlled by supporting an exhaust baffle within a flow path of the process gas being evacuated from the interior space through the exhaust port.

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer.

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer.

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer. The impurity diffusion stop layer substantially prevents impurities of the substrate and the source and drain regions from diffusing into the channel layer.

Abstract: A photodiode structure includes a photodiode and a concave reflector disposed below the photodiode. The concave reflector is arranged to reflect incident light from above back toward the photodiode.

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer. The impurity diffusion stop layer substantially prevents impurities of the substrate and the source and drain regions from diffusing into the channel layer.

Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

Abstract: A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure embedded in the substrate, a stressor embedded in the substrate, and a conductive plug over and electrically coupled with the stressor. A same-material region is sandwiched by the STI structure and an entire sidewall of the stressor, and the same-material region is a continuous portion of the substrate.

Abstract: A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure embedded in the substrate, a stressor embedded in the substrate, and a conductive plug over and electrically coupled with the stressor. A same-material region is sandwiched by the STI structure and an entire sidewall of the stressor, and the same-material region is a continuous portion of the substrate.

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract: A backside illuminated CMOS image sensor comprises an extended photo active region formed over a substrate using a first high energy ion implantation process and an isolation region formed over the substrate using a second high energy ion implantation process. The extended photo active region is enclosed by the isolation region, which has a same depth as the extended photo active region. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.

Abstract: A photodiode structure includes a photodiode and a concave reflector disposed below the photodiode. The concave reflector is arranged to reflect incident light from above back toward the photodiode.

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract: The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.