Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

Abstract: The present disclosure provides a buffer circuit comprising a plurality of operational amplifiers and a switch module. Each operational amplifier forms a buffer. The operational amplifier has an output stage. The stage has a first transistor and a second transistor. The first transistor and the second transistor are connected to an output terminal. The first transistor has a first control terminal. The second transistor has a second control terminal. The switch module is connected to the first control terminal of the first transistor and the second control terminal of the second transistor. The switch module connects together at least two of the first terminals of the first transistor according to a control signal. The switch module connects together at least two of the second terminals of the second transistor according to the control signal.

Abstract: The present disclosure provides a buffer circuit comprising a plurality of operational amplifiers and a switch module. Each operational amplifier forms a buffer. The operational amplifier has an output stage. The stage has a first transistor and a second transistor. The first transistor and the second transistor are connected to an output terminal. The first transistor has a first control terminal. The second transistor has a second control terminal. The switch module is connected to the first control terminal of the first transistor and the second control terminal of the second transistor. The switch module connects together at least two of the first terminals of the first transistor according to a control signal. The switch module connects together at least two of the second terminals of the second transistor according to the control signal.

Abstract: A liquid crystal display (LCD) apparatus includes: multiple differential amplifier stages each of which is operable to generate, according to a bias current and an input voltage, an output voltage having a magnitude and a slew rate that correspond respectively to the input voltage and a magnitude of the bias current, and serving as a data voltage of a corresponding pixel unit of an LCD panel; multiple current sources controllable to generate and provide a plurality of the bias currents to the differential amplifier stages, respectively; and a bias voltage generating unit connected electrically to the current sources in a current mirror configuration for generating an input bias current and controlling the current sources to generate the bias currents according to a latch pulse signal. The slew rate of the output voltage corresponds to a logic state of the input bias current.

Abstract: A display panel driver circuit includes multiple drivers adapted for cooperatively driving a display panel and each operable under a protection mode, and an overheat protection device including multiple protection circuits, each of which controls a respective one of the drivers to operate under the protection mode in response to receipt of an enable signal, an interface circuit which transmits the enable signal to each of the protection circuits in response to receipt of a warning signal, and multiple temperature detection circuits, each of which is able to detect a temperature associated with a respective one of the drivers, and outputs the warning signal to the interface circuit based on the temperature thus detected.

Abstract: A display panel driver circuit includes multiple drivers adapted for cooperatively driving a display panel and each operable under a protection mode, and an overheat protection device including multiple protection circuits, each of which controls a respective one of the drivers to operate under the protection mode in response to receipt of an enable signal, an interface circuit which transmits the enable signal to each of the protection circuits in response to receipt of a warning signal, and multiple temperature detection circuits, each of which is able to detect a temperature associated with a respective one of the drivers, and outputs the warning signal to the interface circuit based on the temperature thus detected.

Abstract: A signal level shifting circuit, including an input stage circuit and an output signal latching circuit. The input stage circuit receives an input signal, wherein a voltage level of the input signal falls within a first predetermined voltage range. The output signal latching circuit is cascoded with the input stage circuit, and includes: a latching circuit for generating an output signal according to the input signal, wherein a voltage level of the output signal falls within a second predetermined voltage range, and the second predetermined voltage range is different from the first predetermined voltage range; and an activating circuit, coupled to the latching circuit, for selectively enabling or disabling the latching circuit, wherein when a level transition appears to the input signal, the activating circuit disables the latching circuit.

Abstract: A clock recovery circuit comprising an initial delay select circuit, a delay locked loop and a clock synthesizer circuit is provided. The initial delay select circuit comprises an initial timing generator, a first multiplexer and an initial value generator. The delay locked loop comprises a delay chain, a phase detector, a counter, and a decoder circuit. The delay locked loop delays an input clock signal to generate a first delay signal and several unit delay signals. The initial value generator receives the unit delay signals to generate an initial value used as an initial counting value of the delay locked loop to prevent harmonic lock. The delay locked loop controls the phase difference between the input clock signal and the first delay signal. The output clock signal of the clock recovery circuit is generated by the clock synthesizer circuit based on the input clock signal and the first delay signal.

Abstract: A clock recovery circuit comprising an initial delay select circuit, a delay locked loop and a clock synthesizer circuit is provided. The initial delay select circuit comprises an initial timing generator, a first multiplexer and an initial value generator. The delay locked loop comprises a delay chain, a phase detector, a counter, and a decoder circuit. The delay locked loop delays an input clock signal to generate a first delay signal and several unit delay signals. The initial value generator receives the unit delay signals to generate an initial value used as an initial counting value of the delay locked loop to prevent harmonic lock. The delay locked loop controls the phase difference between the input clock signal and the first delay signal. The output clock signal of the clock recovery circuit is generated by the clock synthesizer circuit based on the input clock signal and the first delay signal.