Abstract: An interface for a semiconductor chip provided herein includes bonds. The interface has device layout channels and via layout channels and including a circuitry and routing structure. Each device layout channel is located between two via layout channels in a first direction to form a unit layout channel extending in a second direction intersecting the first direction. The bonds are arranged in a bond map following the via layout channels and outside the device layout channels. Most adjacent two of the bonds in the second direction are arranged in a vertical pitch, two bonds at two opposite sides of the device layout channel in the first direction are arranged in a transversal pitch, and the transversal pitch is greater than the vertical pitch. A portion of the circuitry and routing structure is disposed in the device layout channels. A semiconductor device including stacked semiconductor chips is also provided.

Abstract: A non-volatile memory includes a memory unit. The memory unit includes a first word line, a second word line, a control line, a logic circuit, a bit line, a first cell, and a second cell. The logic circuit has a first input terminal connected to the first word line, a second input terminal connected to the second word line, and an output terminal connected to the control line. The first cell has a control terminal connected to the first word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. The second cell has a control terminal connected to the second word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line.

Abstract: A combo memory cell having a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.

Abstract: A combo memory cell comprising a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.

Abstract: A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.

Abstract: A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.

Abstract: A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. An insulating layer is deposited over a thermal oxide layer provided overlying a silicon semiconductor substrate. A contact opening is etched through the insulating layer and the thermal oxide layer to the silicon substrate. The contact opening is overetched whereby a shallow trench is formed within the silicon substrate underlying the contact opening wherein the shallow trench has a bottom and sidewalls comprising the silicon substrate. A first metal layer is deposited over the insulating layer and within the contact opening and within the shallow trench.

Abstract: An apparatus for reading a ROM device. A ROM memory cell's value is determined by comparing the output current from the circuit with a reference current. The output current from a memory cell is outputted to a current conveyor with a reference current and then inputted to a difference sense amplifier which compares the output current with the reference current and amplifies the difference. If a memory cell is programmed the transistor in the memory cell will draw current away from the current source reducing the output current. This will cause the programmed memory cell current to be of a lesser value than a reference current. If a memory cell has been programmed the transistor will not draw any current and therefore the output current will be a greater value than the reference current. Two extra transistors can be added to adjust the current level on reference bitline.

Abstract: An apparatus for reading a ROM device. A ROM memory cell's value is determined by comparing the output current from the circuit with a reference current. The output current from a memory cell is outputted to a current conveyor with a reference current and then inputted to a difference sense amplifier which compares the output current with the reference current and amplifies the difference. If a memory cell is programmed the transistor in the memory cell will draw current away from the current source reducing the output current. This will cause the programmed memory cell current to be of a lesser value than a reference current. If a memory cell has been programmed the transistor will not draw any current and therefore the output current will be a greater value than the reference current. Two extra transistors can be added to adjust the current level on reference bitline.

Abstract: A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. A thermal oxide layer is provided overlying a silicon semiconductor substrate. An insulating layer is deposited overlying the thermal oxide layer. A contact opening is etched through the insulating layer and the thermal oxide layer to the silicon substrate. The contact opening is overetched whereby a shallow trench is formed within the silicon substrate underlying the contact opening wherein the shallow trench has a bottom and sidewalls comprising the silicon substrate. A first metal layer is deposited over the insulating layer and within the contact opening and within the shallow trench.

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Abstract: A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. The method provides a simple and effective method for decreasing the possibility of forming a bad Schottky diode.

Abstract: A method is disclosed for improving the bonding strength of wire bonds on semiconductor chips. Aluminum-silicon-copper is employed as the metal for wire bonding-pads. Openings are formed in the passivation layer over the bonding-pads. The exposed metal in the openings is treated with a fluorine containing F-plasma. A thin passivation film, with C, F, and O content is formed over the metal bonding pads. This protective film prevents the formation of pitting and staining of the bonding-pads when the wafer is subjected to repeated developing solutions during the color filter process performed for the CMOS image sensors, for example. Consequently, the wire bonds formed during the packaging of the chips are stronger and more reliable.

Abstract: A method for stripping positive photoresist from a keyhole 17 in a passivation layer 18 before a heating process using NMP solvent strips after a photoresist strip. The process is summarized by the 5 steps as follows: (1) Photoresist strip 1 (e.g., EKC 830), (2) Photoresist strip 2 (e.g., EKC 830 photoresist stripper), (3) N-methly-2-pyrolidone (NMP) solvent strip-agitated (solvent is preferably the same solvent in the photoresist stripper (1 &2) (4) NMP solvent strip-agitated and (5) H.sub.2 O rinse. The NMP solvent strip steps (3) and (4) remove photoresist residue (16, FIG. 1) in the key hole 17. This prevents the formation of photoresist extrusions 24 while annealing the metal lines 14.