Patents by Inventor Chih-Kang Yeh

Chih-Kang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200401322
    Abstract: A valid data merging method, a memory control circuit unit, and a memory storage device are provided. The method includes: obtaining a first system parameter corresponding to a first region and a second system parameter corresponding to a second region; determining whether the first system parameter is greater than the second system parameter; selecting a third physical erasing unit from the second region preferentially and performing a valid data merging operation by using the third physical erasing unit when the first system parameter is greater than the second system parameter; and selecting a fourth physical erasing unit from the first region preferentially and performing the valid data merging operation by using the fourth physical erasing unit when the first system parameter is not greater than the second system parameter.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 24, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10872656
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: writing a first data and a second data to a first physical erasing unit; copying the first data from the first physical erasing unit to a second physical erasing unit; and copying the second data from the first physical erasing unit to a third physical erasing unit, wherein the memory sub-module to which the second physical erasing unit belongs is different from the memory sub-module to which the third physical erasing unit belongs.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20200393989
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The memory control method includes: performing a first write operation to write first data to a first physical unit in a first physical group through a first channel; performing a limited data collection operation to collect second data, wherein the limited data collection operation limits that the second data does not include data to be collected from the first physical group after the first write operation is completed; and performing a second write operation during a period of performing the first write operation, so as to write the second data to a second physical unit in the second physical group through a second channel. In addition, the limited data collection operation and the second write operation are configured to release at least one spare physical unit.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 17, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20200388318
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: writing a first data and a second data to a first physical erasing unit; copying the first data from the first physical erasing unit to a second physical erasing unit; and copying the second data from the first physical erasing unit to a third physical erasing unit, wherein the memory sub-module to which the second physical erasing unit belongs is different from the memory sub-module to which the third physical erasing unit belongs.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 10, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10824368
    Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a first write command from a host system; determining whether to write a first data corresponding to the first write command by using a first mode or write the first data by using a second mode according to an available buffer memory state; writing the first data into a first physical erasing unit among a plurality of physical erasing units by using the first mode when the first data is determined to be written by using the first mode; and writing the first data into a second physical erasing unit among the physical erasing units by using the second mode when the first data is determined to be written by using the second mode.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: November 3, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10824340
    Abstract: A memory management method is provided according to an exemplary embodiment. The method includes: receiving a write command and determining whether a usage status of physical units associated to a storage area conforms to a first predetermined status; storing write data corresponding to the write command to at least one of physical units associated to a temporary area if the usage status of the physical units associated to the storage area conforms to the first predetermined status; associating the at least one physical unit storing the write data to the storage area; and allocating at least one logical unit to map the at least one physical unit associated to the storage area.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 3, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10782920
    Abstract: A data access method, a memory storage apparatus and a memory control circuit unit are provided. The memory storage apparatus includes a rewritable non-volatile memory module and the memory control circuit unit for controlling the rewritable non-volatile memory module. The data access method includes: receiving an access command; detecting a temperature of the memory storage apparatus; determining whether the temperature of the memory storage apparatus is lower than a first threshold; if the temperature of the memory storage apparatus is lower than the first threshold, performing a dummy access command or adjusting an operating voltage. The data access method further includes performing the access command after the dummy access command is performed or the operating voltage is adjusted.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: September 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20200186171
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Chih-Kang Yeh
  • Patent number: 10678698
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The data writing method includes transmitting a command to a host system to obtain a plurality of data, wherein the plurality of data are arranged in a sequence order in the host system, obtaining first data among the plurality of data and obtaining second data after obtaining the first data. The method further includes writing the first data to a corresponding physical page on a first word line among a plurality of word lines, and writing the second data to another corresponding physical page on a second word line among the plurality of word lines, wherein the first and second word lines belong to first and second memory sub-modules, and the first data and the second data are discontinuously arranged in the sequence order. The first and second data may each comprise sub-data, and the sub-data may be written into physical pages on the first and second word lines.
    Type: Grant
    Filed: September 17, 2017
    Date of Patent: June 9, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20200133835
    Abstract: A data storing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a first data; determining whether a wear degree value of a rewritable non-volatile memory module is less than a threshold; if the wear degree value of the rewritable non-volatile memory module is less than the threshold, storing the first data into the rewritable non-volatile memory module by using a first mode; and if the wear degree value of the rewritable non-volatile memory module is not less than the threshold, storing the first data into the rewritable non-volatile memory module by using a second mode. A reliability of the first data stored by using the first mode is higher than a reliability of the first data stored by using the second mode.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 30, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10620858
    Abstract: A data storage method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a first space in a first physical unit of a rewritable non-volatile memory module; and storing at least part of data stored in at least one physical unit of the rewritable non-volatile memory module to a second space in the first physical unit, and the second space is not belonging to the first space, and the first space is for ensuring that valid data stored in at least one second physical unit among the at least one physical unit can be stored to the first physical unit. Therefore, it is ensured that at least one spare physical unit of the memory storage device can be released by a data merging operation of multiple source nodes.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20200097217
    Abstract: A data access method, a memory storage apparatus and a memory control circuit unit are provided. The memory storage apparatus includes a rewritable non-volatile memory module and the memory control circuit unit for controlling the rewritable non-volatile memory module. The data access method includes: receiving an access command; detecting a temperature of the memory storage apparatus; determining whether the temperature of the memory storage apparatus is lower than a first threshold; if the temperature of the memory storage apparatus is lower than the first threshold, performing a dummy access command or adjusting an operating voltage. The data access method further includes performing the access command after the dummy access command is performed or the operating voltage is adjusted.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 26, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10592167
    Abstract: An exemplary embodiment of the disclosure provides a data merge method for a memory storage device. The method comprises: performing a data merge operation to store valid data collected from a source node comprising at least one first physical unit to a recycling node comprising a second physical unit. The data merge operation comprises: reading a first data from the at least one first physical unit by a first reading operation; performing a first stage programming operation on the second physical unit according to the first data; reading the first data from the at least one first physical unit again by a second reading operation after the first stage programming operation is performed; and performing a second stage programming operation on the second physical unit according to the first data read by the second reading operation.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 17, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20200073792
    Abstract: Exemplary embodiments of the disclosure provide a memory management method for a rewritable non-volatile memory module including the following steps. A host write operation is performed to receive a write command from a host system and store a first data corresponding to the write command to a first physical unit. A first updating data corresponding to the host write operation is recorded. A data merge operation is performed to read a second data from a second physical unit and store the second data to a third physical unit. A second updating data corresponding to the data merge operation is recorded. A management information is read from the rewritable non-volatile memory module to a buffer memory and updated in the buffer memory according to the first updating data and the second updating data.
    Type: Application
    Filed: October 24, 2018
    Publication date: March 5, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20200065187
    Abstract: A data access method, a memory control circuit unit and a memory storage device are provided. The method includes generating a first error correction code corresponding to received first data according to a first error correction encoding operation; and generating a second error correction code corresponding to received second data according to a second error correction encoding operation, wherein the second error correction code includes a first and a second partial error correction code. The method further includes writing the first data, the first error correction code and the second partial error correction code to a data bit area and a redundant bit area of a first physical programming unit respectively; and writing the second data and the first partial error correction code to the data bit area and the redundant bit area of a second physical programming unit respectively.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 27, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10565052
    Abstract: A data protecting method, a memory control circuit unit and a memory storage apparatus are provided. The method includes generating a first temporary parity code group based on first data written into a first super physical unit; generating a second temporary parity code group by performing a logic operation on second data written into a second super physical unit and the first temporary parity code group; and generating an updated parity code group by performing the logic operation on the second temporary parity code group and the first data when data of the first super physical unit all become invalid data.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 18, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20200050399
    Abstract: An exemplary embodiment of the disclosure provides a data merge method for a memory storage device. The method comprises: performing a data merge operation to store valid data collected from a source node comprising at least one first physical unit to a recycling node comprising a second physical unit. The data merge operation comprises: reading a first data from the at least one first physical unit by a first reading operation; performing a first stage programming operation on the second physical unit according to the first data; reading the first data from the at least one first physical unit again by a second reading operation after the first stage programming operation is performed; and performing a second stage programming operation on the second physical unit according to the first data read by the second reading operation.
    Type: Application
    Filed: September 26, 2018
    Publication date: February 13, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10503433
    Abstract: The disclosure provides a memory management method, which includes: selecting at least one logical unit mapped to physical units programmed based on a first operating mode; determining a reference count according to a number of the selected logical unit; receiving a first write command; determining whether the reference count is greater than a threshold value; if the reference count is greater than the threshold value, programming first data into a first physical unit based on the first operating mode, and each memory cell in the first physical unit stores a first number of bit data; if the reference count is not greater than the threshold value, programming the first data into a second physical unit based on a second operating mode, and each memory cell in the second physical unit stores a second number of bit data, and the second number is greater than the first number.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 10, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10459630
    Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: defining a first data management rule for a first type physical unit and a second data management rule for a second type physical unit, and a data density of the first type physical unit is lower than the data density of the second type physical unit; if a first physical unit belongs to the first type physical unit, managing the first physical unit according to the first data management rule to make the data stored in the first physical unit conforming to a first reliability level; and if the first physical unit belongs to the second type physical unit, managing the first physical unit according to the second data management rule to make the data stored in the first physical unit conforming to a second reliability level.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: October 29, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10423524
    Abstract: A memory storage device, a memory control circuit unit and a data storage method for a rewritable non-volatile memory module are disclosed. The method includes: receiving first data; mapping a logical unit of the first data to a first physical unit in a first management unit and not storing the first data to the rewritable nonvolatile memory module if a data content of the first data is identical to a data content of second data stored in the first physical unit. The method also includes storing logical-to-physical bit map information to a second physical unit in the first management unit, wherein the logical-to-physical bit map information corresponds to at least one logical-to-physical mapping table and is configured for identifying valid data in the first management unit. Identifiers or symbols of data content may be compared to determine if first and second data are identical.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: September 24, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh