Abstract: Methods, systems, and computer programs are presented for networking communications. One method includes an operation for receiving a packet in a first format by a virtual driver providing a communications interface of a first type (CI1), the first format being for CI1. Further, the method includes an operation for encapsulating the packet in a second format by a processor, the second format being for a communications interface of a second type (CI2) different from CI1. In addition, the method includes an operation for sending the encapsulated packet in the second format to a switch module. The switch module includes a switch fabric, one or more CI1 ports, and one or more CI2 ports, and the switch module transforms the packet back to the first format to send the packet in the first format to a CI1 network via one of the CI1 ports in the switch module.

Abstract: One networking device includes a switch module, a server, and a switch controller. The switch module has ports with a communications interface of a first type (CI1) and ports with a communications interface of a second type (CI2). The server, coupled to the switch module via a first CI2 coupling, includes a virtual CI1 driver, which provides a CI1 interface in the server, defined to exchange CI1 packets with the switch module via the first CI2 coupling. The virtual CI1 driver includes a first network device operating system (ndOS) program. The switch controller, in communication with the switch module via a second CI2 coupling, includes a second ndOS program controlling, in the switch module, a packet switching policy defining the switching of packets through the switch module or switch controller. The first and second ndOS programs exchange control messages to maintain a network policy for the switch fabric.

Abstract: One networking device includes a switch module, a server, and a switch controller. The switch module has ports with a communications interface of a first type (CI1) and ports with a communications interface of a second type (CI2). The server, coupled to the switch module via a first CI2 coupling, includes a virtual CI1 driver, which provides a CI1 interface in the server, defined to exchange CI1 packets with the switch module via the first CI2 coupling. The virtual CI1 driver includes a first network device operating system (ndOS) program. The switch controller, in communication with the switch module via a second CI2 coupling, includes a second ndOS program controlling, in the switch module, a packet switching policy defining the switching of packets through the switch module or switch controller. The first and second ndOS programs exchange control messages to maintain a network policy for the switch fabric.

Abstract: Methods, systems, and computer programs are presented for networking communications. One method includes an operation for receiving a packet in a first format by a virtual driver providing a communications interface of a first type (CI1), the first format being for CI1. Further, the method includes an operation for encapsulating the packet in a second format by a processor, the second format being for a communications interface of a second type (CI2) different from CI1. In addition, the method includes an operation for sending the encapsulated packet in the second format to a switch module. The switch module includes a switch fabric, one or more CI1 ports, and one or more CI2 ports, and the switch module transforms the packet back to the first format to send the packet in the first format to a CI1 network via one of the CI1 ports in the switch module.

Abstract: Systems are presented for processing packets in a network switch. One network device includes a processor, an Ethernet switch, a PCIe switch, and a packet processor. The processor is for executing a controller program, and the Ethernet switch is for switching packets among a ports. Further, the PCIe switch is coupled to the processor and the Ethernet switch, and the packet processor, coupled to the Ethernet switch and the PCIe switch, is operable to modify an application header of an incoming packet and send the incoming packet to one of the ports. The controller program is operable to configure the Ethernet switch and the packet processor to define processing of packets. The controller program is operable to send a first configuration rule to the Ethernet switch, the first configuration rule defining that packets of a network flow requiring header modification be forwarded to the packet processor.

Abstract: In general, the invention relates to a network device that includes a port configured to receive a packet and a packet processor (PP) configured to receive the packet from the port, in response to receiving the packet, make a first determination that a trigger condition exists, and in response to the first determination, issue a configuration action, where the configuration action, when performed by the network device, modifies a configuration of a component on the network device.

Abstract: In general, in one aspect, the invention relates to a network device, including: an input port; an output port; a switch fabric including a primary fabric, an auxiliary fabric, and a controller; and a distributor configured to obtain, from the input port, a first data unit, provide the first data unit to the primary fabric, determine, after the first data unit is transmitted to the primary fabric, that the primary fabric is congested, send, in response to determining that the primary fabric is congested, a request to the controller to establish a data path through the auxiliary fabric, obtain, from the input port and after sending the request, a second data unit, provide the second data unit to the auxiliary fabric, where the auxiliary fabric transmits the second data unit to the aggregator through the data path in the auxiliary fabric.

Abstract: Methods, systems, and computer programs are presented for networking communications. One method includes an operation for receiving a packet in a first format by a virtual driver providing a communications interface of a first type (CI1), the first format being for CI1. Further, the method includes an operation for encapsulating the packet in a second format by a processor, the second format being for a communications interface of a second type (CI2) different from CI1. In addition, the method includes an operation for sending the encapsulated packet in the second format to a switch module. The switch module includes a switch fabric, one or more CI1 ports, and one or more CI2 ports, and the switch module transforms the packet back to the first format to send the packet in the first format to a CI1 network via one of the CI1 ports in the switch module.

Abstract: Methods, systems, and computer programs are presented for providing a program to a server. One method includes an operation for receiving a request by a switching device from a first server, the request being for a boot image for booting the first server. In addition, the method includes operations for determining if the boot image is available from non-volatile storage in the switching device, and for forwarding the request to a second server when the boot image is absent from the non-volatile storage. Further, the method includes an operation for sending the boot image to the first server from the switching device when the boot image is available from the non-volatile storage.

Abstract: Methods, systems, and computer programs are presented for managing a switching layer fabric. A network device operating system (ndOS) program includes program instructions for exchanging switching policy regarding a switching of network packets in a plurality of ndOS switching devices having respective ndOS programs executing therein. The first ndOS program is executed in a first ndOS switching device, and the switching policy is exchanged with other ndOS programs via multicast messages. Further, the ndOS program includes program instructions for exchanging resource control messages with the other ndOS switching devices to implement service level agreements in the switching layer fabric, where the ndOS switching devices cooperate to enforce the service level agreements. Further yet, the ndOS program includes program instructions for receiving changes to the switching policy, and program instructions for propagating the received changes to the switching policy via message exchange between the ndOS programs.

Abstract: Methods, systems, and computer programs are presented for switching a network packet. One method includes operations for receiving a packet having a media access control (MAC) address, and for switching the packet by a first packet switching device (PSD) when the MAC address is present in a first memory. Further, the method includes operations for transferring the packet to a second PSD when the MAC address is absent from the first memory and present in a second memory associated with the second PSD, and for transferring the packet to a third PSD when the MAC address is absent from the first memory and the second memory.

Abstract: One networking device includes a switch module, a server, and a switch controller. The switch module has ports with a communications interface of a first type (CI1) and ports with a communications interface of a second type (CI2). The server, coupled to the switch module via a first CI2 coupling, includes a virtual CI1 driver, which provides a CI1 interface in the server, defined to exchange CI1 packets with the switch module via the first CI2 coupling. The virtual CI1 driver includes a first network device operating system (ndOS) program. The switch controller, in communication with the switch module via a second CI2 coupling, includes a second ndOS program controlling, in the switch module, a packet switching policy defining the switching of packets through the switch module or switch controller. The first and second ndOS programs exchange control messages to maintain a network policy for the switch fabric.

Abstract: A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.

Abstract: A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal.

Abstract: A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

Abstract: A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.

Abstract: A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

Abstract: A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal.

Abstract: One embodiment of the present invention provides a system that operatively couples an integrated circuit with a microstrip transmission line through chip lamination. The system includes a first semiconductor die containing the integrated circuit, and a second semiconductor die containing the microstrip transmission line. Unlike metal lines in the integrated circuit, which have relatively small cross-sections, the microstrip transmission line has a cross-section that is large enough so that signal propagation is governed by inductance and capacitance (LC) instead of resistance and capacitance (RC). The first semiconductor die and the second semiconductor die are laminated together so that the integrated circuit on the first semiconductor die is operatively coupled with the microstrip transmission line in the second semiconductor die.