Patents by Inventor Chih-Kung Huang

Chih-Kung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113143
    Abstract: Various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. The first image sensor element is adjacent to the second image sensor element. A first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. A second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 4, 2024
    Inventors: Cheng Yu Huang, Wen-Hau Wu, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chih-Kung Chang
  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11923386
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20230022643
    Abstract: A disclosed semiconductor device includes a package substrate, a first semiconductor die coupled to the package substrate, a package lid attached to the package substrate and covering the semiconductor die, and a thermal interface material located between a top surface of the semiconductor die and an internal surface of the package lid. The semiconductor device may further include a dam formed on the internal surface of the package lid. The dam may constrain the thermal interface material on one or more sides of the first semiconductor die such that the thermal interface material is located within a predetermined volume between the top surface of the first semiconductor die and the internal surface of the package lid during a reflow operation. The package lid may include a metallic material and the dam may include an epoxy material formed as a single continuous structure or may be formed as several disconnected structures.
    Type: Application
    Filed: March 14, 2022
    Publication date: January 26, 2023
    Inventors: Wei Teng CHANG, Meng-Tsung KUO, Chih-Kung HUANG, Hui-Chang YU
  • Publication number: 20220278069
    Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 1, 2022
    Inventors: Meng-Tsung KUO, Hui-Chang YU, Chih-Kung HUANG, Wei-Teng CHANG
  • Patent number: 11328971
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Publication number: 20200357714
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Patent number: 10727147
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Publication number: 20190057916
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Patent number: 10109547
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, LLC
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Publication number: 20170221788
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Application
    Filed: March 17, 2016
    Publication date: August 3, 2017
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Patent number: 9451694
    Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: September 20, 2016
    Assignee: IBIS Innotech Inc.
    Inventors: Chih-Kung Huang, Wei-Jen Lai, Wen-Chun Liu
  • Publication number: 20160034083
    Abstract: A touch sensing device includes a light-transmitting substrate, an edge layer and sensing lines. The light-transmitting substrate has an upper surface and a lower surface opposite to the upper surface, and the edge layer is covered on an edge of the upper surface of the light-transmitting substrate. The edge layer has a main body made of insulated material, and conductive wires. The main body has a first surface attached on the upper surface of the light-transmitting substrate, a second surface opposite and parallel to the first surface, and slots recessed downwardly from the second surface. The conductive wires are embedded in the slots, respectively. The sensing lines are disposed on the upper surface of the light-transmitting substrate and electrically connected with the conductive wires, respectively. Therefore, the touch sensing device can have simple and quick manufacturing process, high yield rate and low cost.
    Type: Application
    Filed: December 23, 2014
    Publication date: February 4, 2016
    Inventors: Wei-Jen LAI, Chih-Kung HUANG
  • Publication number: 20150373849
    Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface.
    Type: Application
    Filed: March 19, 2015
    Publication date: December 24, 2015
    Inventors: Chih-Kung Huang, Wei-Jen Lai, Wen-Chun Liu
  • Publication number: 20150364448
    Abstract: A package structure includes a chip, a selective-electroplating epoxy compound, a patterned circuit layer and a plurality of conductive vias. The chip includes a plurality of solder pads, an active surface and a back surface opposite to the active surface. The solder pads are disposed on the active surface. The selective-electroplating epoxy compound covers the chip and includes non-conductive metal complex. The patterned circuit layer is disposed directly on a surface of the selective-electroplating epoxy compound. The conductive vias are disposed directly at the selective-electroplating epoxy compound to electrically connect the solder pads and the patterned circuit layer.
    Type: Application
    Filed: March 19, 2015
    Publication date: December 17, 2015
    Inventors: Chih-Kung Huang, Wei-Jen Lai, Wen-Chun Liu
  • Publication number: 20150061814
    Abstract: A ferrite circuit board includes a substrate and a wire. The substrate is made of ferrite and provided with a surface and an elongated groove recessed from the surface. The elongated groove has an inner wall having a roughness Ra ranging from 0.1 ?m to 20 ?m. The wire is embedded in the elongated groove of the substrate, such that the wire is not easily separated from the substrate. The ferrite circuit board can be used as an inductor to provide abundant functionality.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 5, 2015
    Inventors: Wei-Jen LAI, Chih-Kung HUANG
  • Publication number: 20130213698
    Abstract: A holder includes a main body on which a plurality of circuit lines are laid out. The main body is integrally molded from a plastic material and can be formed thereon with a circuit layout by a specific process, such as a laser activated and chemical plating process. The main body includes a chamber having an opening formed at the top side of the main body, a base surface, and a stepped wall. Each of the circuit lines is arranged on the stepped wall of the chamber stereoscopically. Thus, the holder does not need to make a hole running therethrough to reach electrical connection between surfaces of different heights. Besides, the circuit lines are arranged stereoscopically, so they can extend to the top and bottom sides of the holder. Therefore, the holder can be applied to not only the traditional package but an upside-down package.
    Type: Application
    Filed: July 3, 2012
    Publication date: August 22, 2013
    Applicant: DOMINTECH CO., LTD
    Inventors: Jeff BIAR, Chih-Kung Huang, Ming-Ching Wu
  • Patent number: 8468888
    Abstract: A MEMS sensor capable of sensing acceleration and pressure includes a frame, a proof mass and flexible bridges connected between the frame and the proof mass in such a way that the proof mass is moveably suspended inside the frame. The proof mass is provided with a pressure sensing diaphragm and a sealed chamber corresponding to the diaphragm such that the proof mass is not only served as a moveable sensing element for acceleration measurement but also a pressure sensing element.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: June 25, 2013
    Assignees: Domintech Co., Ltd.
    Inventors: Ming-Ching Wu, Chih-Kung Huang, Jeff Biar, Kazuhiro Okada
  • Publication number: 20120099285
    Abstract: A substrate for chip packaging includes a laminated board made of a plurality of ferrite sheets and a coil component disposed on the board. The coil component includes a first coil conductor, a second coil conductor, and a first via-hole conductor. The first coil conductor is disposed on a surface of a first sheet of the board. The second coil conductor is disposed on a surface of a second sheet of the board. The first via-hole conductor includes a first through hole formed at the first sheet and a first conductor filled in the first through hole. The substrate further includes a top surface having a plurality of first conductive pads, and a bottom surface having a plurality of second conductive pads. Each of the first conductive pads is electrically connected with each of the second conductive pads.
    Type: Application
    Filed: January 26, 2011
    Publication date: April 26, 2012
    Inventors: Jeff BIAR, Chih-Kung HUANG
  • Publication number: 20120060605
    Abstract: A MEMS sensor capable of sensing acceleration and pressure includes a frame, a proof mass and flexible bridges connected between the frame and the proof mass in such a way that the proof mass is moveably suspended inside the frame. The proof mass is provided with a pressure sensing diaphragm and a sealed chamber corresponding to the diaphragm such that the proof mass is not only served as a moveable sensing element for acceleration measurement but also a pressure sensing element.
    Type: Application
    Filed: November 22, 2010
    Publication date: March 15, 2012
    Inventors: Ming-Ching WU, Chih-Kung Huang, Jeff Biar, Kazuhiro Okada