Abstract: A method of reconstructing transcranial images using a dual-mode ultrasonic phased array includes steps of: controlling channels to emit energy toward an intracranial target point of a patient; respectively generating backscattered radiofrequency (RF) data by using the channels to receive backscattered energy reflected from the intracranial target; and reconstructing an acoustic distribution image based on those backscattered RF data in real-time. Compared with Pre-Treatment Ray Tracing Method, the present invention can display intracranial pressure distribution in real-time; compared with MR Thermometry, the present invention can be applied to low-energy applications without temperature change; and compared with Passive Cavitation Imaging, the present invention can stably present acoustic distribution images without relying on microbubbles.

Abstract: A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.

Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.

Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.

Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.

Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

Abstract: A power consumption monitoring device includes a sensor, a storage, and a processor. The sensor is configured to detect a power-consuming device quantity and a power consumption amount. The storage is configured to store the power-consuming device quantity and the power consumption amount. The processor is communicatively connected to the sensor and the storage. The processor is configured to calculate a power-consuming device idling indicator based on the power-consuming device quantity and the power consumption amount in a monitoring time interval, wherein the power-consuming device idling indicator is used for indicating a deviation status of the power-consuming device quantity and the power consumption amount. The processor is further configured to determine whether the power-consuming device idling indicator exceeds a warning threshold. In response to the power-consuming device idling indicator exceeding the warning threshold, the processor is further configured to generate a warning message.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

Abstract: The present disclosure discloses a method and a device for optical proximity effect correction, wherein the method for the optical proximity effect correction comprises: acquiring an original target pattern and preprocessing the original target pattern to form a secondary target pattern so that the secondary target pattern meets a preset processing rule: performing optical proximity effect correction on the secondary target pattern to acquire a corrected pattern; acquiring a simulated contour of the original target pattern based on the corrected pattern; calculating a deviation between the simulated contour and the original target pattern; and judging whether the corrected pattern meets the processing requirements based on the deviation value. The present disclosure provides the method and the device for optical proximity effect correction to solve the existing problem of serious distortion of photo-etched patterns after the optical proximity effect correction.

Abstract: Methods are provided for identifying candidate agents for use in inhibiting expression of certain receptors and ion channels in nociceptors. Also provided are methods for identifying candidates agents for use in inhibiting neurophathic and other types of pain.

Abstract: A UV light generator for receiving a baseband light beam from a baseband light source is provided. The UV light generator includes a first lens unit, a second lens unit, a first frequency doubling crystal and a second frequency doubling crystal. The baseband light beam from the baseband light source passes through the first lens unit. The first lens unit and the second lens unit control a minimum of baseband light spot position and a minimum of second harmonic light spot position. The first frequency doubling crystal is disposed between the first lens unit and the second lens unit, and located on the minimum of baseband light spot position. The second frequency doubling crystal is disposed between the first lens unit and the second lens unit, and located on the minimum of second harmonic light spot position.

Abstract: A UV light generator for receiving a baseband light beam from a baseband light source is provided. The UV light generator includes a first lens unit, a second lens unit, a first frequency doubling crystal and a second frequency doubling crystal. The baseband light beam from the baseband light source passes through the first lens unit. The first lens unit and the second lens unit control a minimum of baseband light spot position and a minimum of second harmonic light spot position. The first frequency doubling crystal is disposed between the first lens unit and the second lens unit, and located on the minimum of baseband light spot position. The second frequency doubling crystal is disposed between the first lens unit and the second lens unit, and located on the minimum of second harmonic light spot position.

Abstract: An attenuating PSM includes a quartz substrate, a first dummy pad pattern disposed on the quartz substrate, wherein the first dummy pad pattern is composed of a first phase shifter material layer with a transmission rate of greater than or equal to 15%, and a first opaque pattern disposed at a center area of the first dummy pad pattern. The first opaque pattern has a shape that is analogous to the first dummy pad pattern and surface area of the first opaque pattern is smaller than that of the first dummy pad pattern.

Abstract: A high power LED has at least a porous material layer, a thermal conductive layer and a chip. The thermal conductive layer is disposed on the surface of the porous material layer and the chip is disposed on the thermal conductive layer. Heat generated by the chip is conducted from the thermal conductive layer to the porous material layer, and convected outside via the porous material layer. Thereby, surface area in contact with the air is increased and high thermal conductivity and high heat convection are also achieved.

Abstract: Methods are provides for identifying candidate agents for use in inhibiting expression of certain receptors and ion channels in nociceptors. Also provided are methods for identifying candidates agents for use in inhibiting neurophathic and other types of pain.

Abstract: An attenuating PSM includes a quartz substrate, a first dummy pad pattern disposed on the quartz substrate, wherein the first dummy pad pattern is composed of a first phase shifter material layer with a transmission rate of greater than or equal to 15%, and a first opaque pattern disposed at a center area of the first dummy pad pattern. The first opaque pattern has a shape that is analogous to the first dummy pad pattern and surface area of the first opaque pattern is smaller than that of the first dummy pad pattern.

Abstract: A phase shift mask comprises a glass substrate with a surface and a metal layer. The glass substrate comprises a first phase section, a second phase section and a border section. The metal layer is covered on the glass substrate and defining a pattern comprising a plurality of parallel lines, the first phase section and the second phase section. The terminal of at least one of the lines is not rectangular and a distance between the tips of the lines in the first phase section are defined to be not less than the width of the first phase section.